Active-matrix substrate, display panel and display device including the same

ABSTRACT

A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate ( 20   a ) are provided gate lines ( 13 G) and source lines. On the active-matrix substrate ( 20   a ) are further provided: gate drivers ( 11 ) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line ( 13 G); and lines ( 15 L 1 ) each for supplying a control signal to the associated gate driver ( 11 ). A control signal is supplied by a display control circuit ( 4 ) located outside the display region to the gate drivers ( 11 ) via the lines ( 15 L 1 ). In response to a control signal supplied, each gate driver ( 11 ) drives the gate line ( 13 G) to which it is connected.

TECHNICAL FIELD

The present invention relates to an active-matrix substrate, a displaypanel and a display device including the same, and, more particularly,to the arrangement of gate drivers.

BACKGROUND ART

Display panels are known where gate drivers are provided along a side ofan active-matrix substrate and source drivers are provided along anadjacent side thereof. JP 2004-538511 A discloses a technique toprovide, along one side of the pixel element array, a row drivingcircuit for driving column address conductors for supplying data signalsand a column driving circuit for driving row address conductors forsupplying row selection signals. Thus, JP 2004-538511 A prevents thesedriving circuits from limiting the region around the pixel element arrayon the support body that holds the pixel element array and othercomponents.

DISCLOSURE OF THE INVENTION

When a potential corresponding to a selection or non-selection state ofa gate line is supplied to a gate line through one side of theactive-matrix substrate that is parallel to the source lines, thepotential becomes dull as it goes toward the distal end of the gateline. This requires a design that takes into consideration the positionwhere a potential on a gate line becomes dull. JP 2004-538511 A,mentioned above, provides the gate driver and source driver along oneside of the active-matrix substrate to make it possible to reduce thewidth of the portions of the picture frame region along the other threesides. However, according to JP 2004-538511 A, the distance of routingof the gate lines is greater than in conventional devices, increasingthe load on the gate lines. As a result, a potential provided to a gateline becomes dull, making it difficult to drive the gate lines at highspeed.

An object of the present invention is to provide a technique to reducedullness of a potential provided to a line such as a gate line on theactive-matrix substrate to enable driving the line at high speed and, atthe same time, reduce the width of the picture frame region.

An active-matrix substrate according to a first invention includes: aplurality of data lines; a plurality of lines crossing the plurality ofdata lines and including at least gate lines; and a driving circuitconnected with at least one of the plurality of lines for controlling apotential of this line in response to a control signal supplied fromoutside a display region that includes pixel regions defined by the datalines and the gate lines, the driving circuit including a plurality ofswitching elements, at least one of the plurality of switching elementsbeing located in one of the pixel regions.

In a second invention, starting from the first invention, the drivingcircuit is connected with one of the gate lines and controls thepotential of this gate line by applying one of a selection voltage and anon-selection voltage to the gate line in response to the controlsignal.

A third invention, starting from the first or second invention, furtherincludes: a first terminal located outside the display region forsupplying a data signal to one of the plurality of data lines; and asecond terminal located outside the display region for supplying thecontrol signal to the driving circuit, the first and second terminalsbeing located outside a side of the display region that is parallel tothe gate lines.

A fourth invention further includes: a pixel electrode located in one ofthe pixel regions of the second or third invention and connected withone of the gate lines and one of the data lines, wherein a shield layermade of transparent conductive film is provided between one of theswitching elements of the driving circuit that is located in the pixelregion, and the pixel electrode.

A fifth invention further includes a pixel electrode located in one ofthe pixel regions of the second or third invention and connected withone of the gate lines and one of the data lines, wherein one of theswitching elements of the driving circuit that is located in the pixelregion is disposed so as not to overlie the pixel electrode.

In a sixth invention, starting from one of the second to fifthinventions, an adjustment line is further provided in a pixel region inwhich the switching element of the driving circuit is not provided suchthat this pixel region has an aperture ratio substantially equal to thatof a pixel region in which a switching element of the driving circuit isprovided.

A seventh invention, starting from one of the third to sixth inventions,further includes: a first insulating layer located between a gate linelayer forming the gate lines and a data line layer forming the datalines; a control signal line located in one of the pixel regions anddisposed in the data line layer so as to be generally parallel to thedata lines for supplying the control signal from the second terminal tothe driving circuit; a second insulating layer having a greaterthickness than the first insulating layer and provided on top of thedata line layer and including a contact hole extending therethrough tothe data line layer; and a conductive layer portion provided in thecontact hole, wherein the control signal line is interrupted at alocation overlying one of the gate lines and portions of the controlline on this interruption are connected via the conductive layer portionin the contact hole of the second insulating layer.

An eighth invention, starting from one of the third to sixth inventions,further includes: a control signal line located in one of the pixelregions for supplying the control signal from the second terminal to thedriving circuit, wherein at least a portion of the control signal lineis disposed to be generally parallel to the data lines and located atgenerally the same distance from two data lines in the pixel region.

A ninth invention, starting from one of the second to eighth inventions,further includes: a pixel switching element located in one of the pixelregions and connected with one of the data lines and one of the gatelines, wherein the gate line has portions with a width smaller than themaximum width of the gate line, one of these portions being locatedbetween the point on the gate line to which a gate terminal of the pixelswitching element is connected and the intersection of the data line andthe gate line, and the other one of the portions being located near theintersection of a portion of the gate line to which the gate terminal isnot connected and the data line.

In a tenth invention, starting from one of the second to ninthinventions, each of the pixel regions corresponds to one of a pluralityof colors, and the driving circuit is provided in a pixel regioncorresponding to one of the plurality of colors.

In an eleventh invention, starting from one of the second to tenthinventions, a pixel region in which a the switching element of thedriving circuit is provided has a larger dimension measured in adirection in which the gate lines extend than other pixel regions.

In a twelfth invention, starting from one of the eighth to eleventhinventions, the pixel region includes a pixel electrode connected withone of the gate lines and one of the data lines; and an auxiliarycapacitance electrode connected with the pixel electrode, and theinvention includes: an auxiliary capacitance line located outside thedisplay region and connected with the auxiliary capacitance electrodefor supplying a predetermined potential to the auxiliary capacitanceelectrode; and a low-impedance line located in the pixel region andconnected with the auxiliary capacitance electrode and connected withthe auxiliary capacitance line.

In a thirteenth invention, starting from one of the second to twelfthinvention, a plurality of driving circuits are provided, each for one ofthe gate lines.

In a fourteenth invention, starting from one of the second to thirteenthinventions, the display region is divided into a plurality ofsub-regions arranged in a direction in which the gate lines arearranged, and a driving circuit provided for a gate line disposed ineach of the plurality of sub-regions applies one of a selection voltageand a non-selection voltage to the gate line at a frequency that isspecified for the sub-region.

In a fifteenth invention, starting from one of the third to thirteenthinventions, N gate lines (N is a natural number) are provided, M drivingcircuits (M is a natural number, M≧2), i.e. a first to Mth drivingcircuits, are provided for each of the gate lines, the M drivingcircuits provided for the nth gate line (1≦n≦N) apply a selectionvoltage to the nth gate line in the order beginning with the firstdriving circuit and ending with the Mth driving circuit, the second oneof the M driving circuits to the Mth drive circuit apply the selectionvoltage to the nth gate line at a time point at which the precedingdriving circuit applies the selection voltage to the n+1th gate line,and the first terminal supplies the data line with a data signal for animage to be written to the pixel region defined by the nth gate line andthe data line at a time point at which the Mth driving circuit appliesthe selection voltage to the nth gate line.

In a sixteenth invention, starting from one of the second to thirteenthinventions, the pixel region includes a plurality of sub-pixel regions,the lines include the gate lines and sub-gate lines, one of thesub-pixel regions includes a pixel electrode connected with one of thegate lines and one of the data lines, the other one of the sub-pixelregions includes a pixel electrode connected with one of the sub-gatelines and the data line and a capacitor connected between this pixelelectrode and the pixel electrode in the one of the sub-pixel regions,the driving circuit includes a sub-gate line driver located in a pixelregion in which the switching element is not provided, and provided forone of the sub-gate lines for applying one of the selection voltage andthe non-selection voltage to the sub-gate line in response to thecontrol signal, and the sub-gate line driver applies the selectionvoltage to the sub-gate line in one horizontal interval after theselection voltage is applied to the gate line.

In a seventeenth invention, starting from one of the second tothirteenth inventions, the pixel region includes a plurality ofsub-pixel regions, the lines include the gate lines, sub-gate lines andauxiliary capacitance lines, the plurality of sub-pixel regions eachinclude a pixel electrode connected with one of the gate lines and oneof the data lines, one of the sub-pixel regions includes an auxiliarycapacitance connected with one of the auxiliary capacitance lines, and aswitching element including a gate terminal connected with one of thesub-gate lines, a source terminal connected with the pixel electrode inthe one of the sub-pixel regions, and a drain terminal connected withthe auxiliary capacitance, the driving circuit includes a sub-gate linedriver located in a pixel region in which the switching element is notprovided, and provided for one of the sub-gate lines for applying one ofthe selection voltage and the non-selection voltages to the sub-gateline, and the sub-gate line driver applies the selection voltage to thesub-gate line in response to the control signal after the selectionvoltage is applied to the gate line.

In an eighteenth invention, starting from one of the second tothirteenth inventions, the pixel region includes a plurality ofsub-pixel regions, the lines include the gate lines, first auxiliarycapacitance lines and second auxiliary capacitance lines, the pluralityof sub-pixel regions each include a pixel electrode connected with oneof the gate lines and one of the data lines, one of the sub-pixelregions includes a first auxiliary capacitance connected with the pixelelectrode in the one of the sub-pixel region and one of the firstauxiliary capacitance lines, the other one of the sub-pixel regionsincludes a second auxiliary capacitance connected with the pixelelectrode in the other one of the sub-pixel regions and one of thesecond auxiliary capacitance line, the driving circuit includes anauxiliary capacitance line control element provided inside the displayregion for controlling a potential of the first auxiliary capacitanceline and a potential of the second auxiliary capacitance line, and theauxiliary capacitance line control element applies voltages to the firstauxiliary capacitance line and the second auxiliary capacitance linesuch that the potential of the first auxiliary capacitance line and thepotential of the second auxiliary capacitance line have opposite phasesafter the selection voltage is applied to the gate line.

In a nineteenth invention, starting from one of the second to thirteenthinventions, the lines include the gate lines and auxiliary capacitancelines, the pixel region includes a pixel electrode connected with one ofthe gate lines and one of the data lines and an auxiliary capacitanceconnected with the pixel electrode and one of the auxiliary capacitancelines, the driving circuit includes auxiliary capacitance line driverseach provided for one of the auxiliary capacitance lines, and theauxiliary capacitance line driver applies a voltage with the samepolarity as the voltage on the data line to the auxiliary capacitanceline in response to the control signal.

In a twentieth invention, starting from one of the second to ninthinventions, the driving circuit is provided in each of K regions (K is anatural number, K≧2) arranged in a direction in which the gate lines ofthe display region extend, each driving circuit being provided for everyK gate lines, driving circuits being provided on different gate lines indifferent regions.

In a twenty-first invention, starting from the twentieth invention, thepixel region corresponds to one of a plurality of colors, and thedriving circuit is provided in a pixel region corresponding to one ofthe plurality of colors.

In a twenty-second invention, starting from the twenty-first invention,a pixel region in which a switching element of the driving circuit isprovided has a larger dimension measured in a direction in which atleast one of the gate line and the data line extends than other pixelregions.

In a twenty-third invention, starting from one of the second tothirteenth inventions, the lines include the gate lines and commonelectrode lines, the pixel region includes a pixel electrode connectedwith one of the gate lines and one of the data lines and an auxiliarycapacitance connected with the pixel electrode and one of the commonelectrode lines, the driving circuit includes common electrode driverseach located in a pixel region in which the switching element is notprovided, and provided for one of the common electrode lines, and thecommon electrode driver applies to the common electrode line a voltagewith a polarity opposite that of the potential of the data line inresponse to the control signal.

In a twenty-fourth invention, starting from one of the first to fourthinventions, the lines include the gate lines and light-emission controllines, the pixel region includes a light-emitting element, an electriccircuit connected with one of the data lines and one of the gate lines,and a light-emission control switching element having a gate terminalconnected with one of the light-emission control lines, a sourceterminal connected with the electric circuit, and a drain terminalconnected with the light-emitting element, the driving circuit includeslight-emission control line drivers each provided for one of thelight-emission control lines for controlling a potential of thelight-emission control line in response to the control signal.

A display panel according to a twenty-fifth invention includes: theactive-matrix substrate of one of the first to twenty-second inventions;a counter-substrate having a color filters and a counter-substrate; anda liquid crystal layer sandwiched between the active-matrix substrateand the counter-substrate.

A twenty-sixth invention includes: the active-matrix substrate of thetwenty-third invention; a counter-substrate having a color filter; and aliquid crystal layer sandwiched between the active-matrix substrate andthe counter-substrate.

In a twenty-seventh invention, at least one element of the drivingcircuit is provided on the active-matrix substrate of the twenty-fifthor twenty sixth invention in a dark-line region that is produceddepending on orientation in the liquid crystal layer within the pixelregion.

A display device according to a twenty-eighth invention includes: thedisplay panel of one of the twenty-fifth to twenty-seventh inventions;and a housing containing the display panel, the housing including afirst cover portion located to overlie a portion of a picture frameregion of the display panel and a portion of the display region andhaving a lens with a viewer's side that is curved in shape, and a secondcover portion covering at least a side of the display panel.

The arrangements of the present invention reduce dullness of a potentialprovided to a line on the active-matrix substrate to enable driving thelines at high speed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view of a liquid crystal display device accordingto a first embodiment.

FIG. 2 is a schematic view of the active-matrix substrate according tothe first embodiment.

FIG. 3 is a schematic view of the active-matrix substrate according tothe first embodiment.

FIG. 4 is an example equivalent circuit of a gate driver according tothe first embodiment.

FIG. 5A is a schematic view of an example arrangement of gate driversaccording to the first embodiment.

FIG. 5B is a schematic view of an example arrangement of gate driversaccording to the first embodiment.

FIG. 5C is a schematic view of an example arrangement of gate driversaccording to the first embodiment.

FIG. 6 is an enlarged plan view of the pixel region in which the TFT-Aof FIG. 5B is provided.

FIG. 7A is a schematic cross-sectional view of a TFT-PIX of FIG. 6 takenalong line I-I.

FIG. 7B is a schematic cross-sectional view of the contact CH1 of FIG. 6taken along line II-II.

FIG. 7C is a schematic cross-sectional view of the TFT-A of FIG. 6 takenalong line III-III.

FIG. 7D is a schematic cross-sectional view of the contact CH2 of FIG. 6taken along line IV-IV.

FIG. 8A is an enlarged plan view of the pixel region 204R of FIG. 5B.

FIG. 8B is an enlarged plan view of the pixel region 205R of FIG. 5B.

FIG. 8C is an enlarged plan view of the pixel region 203R of FIG. 5B.

FIG. 8D is an enlarged plan view of the pixel region 205B of FIG. 5C.

FIG. 8E is an enlarged plan view of the pixel region 203B of FIG. 5B.

FIG. 8F is an enlarged plan view of the pixel regions 201B and 202R ofFIG. 5A.

FIG. 9 is a timing chart showing signals encountered when a gate driverscans a gate line.

FIG. 10A is a schematic diagram of an example arrangement of a gatedriver according to a second embodiment.

FIG. 10B is an enlarged plan view of pixel regions of a gate driverlocated in the display region.

FIG. 11 is a schematic cross-sectional view of a liquid crystal displaydevice according to a third embodiment.

FIG. 12 illustrates how light beams emitted from the display surface ofthe third embodiment advance.

FIG. 13 is a schematic view of an active-matrix substrate according to afourth embodiment.

FIG. 14 illustrates the timing for driving gate lines in the sub-regionsof the fourth embodiment.

FIG. 15 is a timing chart illustrating how data is written into thesub-regions of the fourth embodiment.

FIG. 16 is a timing chart illustrating how data is written into thesub-regions of the fourth embodiment.

FIG. 17 is a schematic view of an active-matrix substrate according to afifth embodiment.

FIG. 18 illustrates the timing for supplying start pulses in the fifthembodiment.

FIG. 19 illustrates the timing for driving gate lines in the fifthembodiment.

FIG. 20 is a enlarged schematic diagram of a pixel shown in FIG. 17.

FIG. 21 is a timing chart illustrating how data is written in the fifthembodiment.

FIG. 22 is a schematic plan view of the pixel region in which aswitching element (TFT-F) is provided according to a sixth embodiment.

FIG. 23 is a schematic cross-sectional view of the contact CH6 of FIG.22 taken along line V-V.

FIG. 24A is an enlarged schematic view of the intersection of a gateline and source line of a seventh embodiment.

FIG. 24B illustrates a variation of a gate line of the seventhembodiment.

FIG. 24C illustrates a variation of a gate line of the seventhembodiment.

FIG. 25A is a schematic plan view of a no-gate-driver region of aneighth embodiment.

FIG. 25B is a schematic view of the liquid crystal display device of anexample application of the eighth embodiment.

FIG. 25C illustrates how pixel potentials change in the exampleapplication of the eighth embodiment.

FIG. 26 shows an equivalent circuit of a pixel of a ninth embodiment.

FIG. 27A schematically illustrates pixel regions in which gate driversand auxiliary capacitance signal lines are provided in the ninthembodiment.

FIG. 27B schematically illustrates gate drivers and pixel regions inwhich auxiliary capacitance signal lines are provided in the ninthembodiment.

FIG. 28 is a timing chart illustrating how a pixel shown in FIG. 26 isdriven.

FIG. 29 shows an equivalent circuit of a pixel of a tenth embodiment.

FIG. 30 shows an equivalent circuit of a CS driver of the tenthembodiment.

FIG. 31A schematically illustrates pixel regions in which CS drivers andgate drivers are provided in the tenth embodiment.

FIG. 31B schematically illustrates pixel regions in which CS drivers andgate drivers are provided in the tenth embodiment.

FIG. 32 is a timing chart illustrating how a CS driver shown in FIG. 30is operated.

FIG. 33A is a timing chart illustrating how a gate driver and CS driverof the tenth embodiment are operated.

FIG. 33B is a timing chart illustrating how a pixel shown in FIG. 29 isdriven.

FIG. 34 shows an equivalent circuit of a pixel according to an eleventhembodiment.

FIG. 35A schematically illustrates pixel regions in which gate drivers11_A of the eleventh embodiment are provided.

FIG. 35B schematically illustrates pixel regions in which gate drivers11_A of the eleventh embodiment are provided.

FIG. 36A schematically illustrates pixel regions in which gate drivers11_B of the eleventh embodiment are provided.

FIG. 36B schematically illustrates pixel regions in which gate drivers11_B of the eleventh embodiment are provided.

FIG. 37 is a timing chart illustrating how sub-pixels are driven in theeleventh embodiment.

FIG. 38 shows an equivalent circuit of a pixel according to a twelfthembodiment.

FIG. 39A schematically illustrates pixel regions in which gate drivers11_1 are provided in the twelfth embodiment.

FIG. 39B schematically illustrates pixel regions in which gate drivers11_1 are provided in the twelfth embodiment.

FIG. 39C schematically illustrates pixel regions in which gate drivers11_2 are provided in the twelfth embodiment.

FIG. 39D schematically illustrates pixel regions in which gate drivers11_2 are provided in the twelfth embodiment.

FIG. 40 is a timing chart illustrating how a pixel of the twelfthembodiment is driven.

FIG. 41 shows an equivalent circuit of a pixel according to a thirteenthembodiment.

FIG. 42 is a schematic cross-sectional view of a pixel shown in FIG. 41.

FIG. 43 shows an equivalent circuit of a gate driver and CS driver ofthe thirteenth embodiment.

FIG. 44A is a schematic diagram of pixel regions in which gate driversand CS drivers are provided of the thirteenth embodiment.

FIG. 44B is a schematic diagram of pixel regions in which gate driversand CS drivers are provided of the thirteenth embodiment.

FIG. 45 is a timing chart illustrating how a gate line and an auxiliarycapacitance line of the thirteenth embodiment are driven.

FIG. 46 is a timing chart illustrating how a pixel of the thirteenthembodiment is driven on a frame-to-frame basis.

FIG. 47 shows an equivalent circuit of a pixel according to a fourteenthembodiment.

FIG. 48 is a schematic cross-sectional view of the pixel of FIG. 47.

FIG. 49 shows an equivalent circuit of a gate driver and COM driver ofthe fourteenth embodiment.

FIG. 50A is a schematic diagram of pixel regions in which gate driversand COM devices are provided in the fourteenth embodiment.

FIG. 50B is a schematic diagram of pixel regions in which gate driversand COM devices are provided in the fourteenth embodiment.

FIG. 51 is a timing chart illustrating how a gate line and a commonelectrode line of the fourteenth embodiment are driven.

FIG. 52 is a timing chart illustrating how a pixel is driven on aframe-to-frame basis in the fourteenth embodiment.

FIG. 53 shows an equivalent circuit of a pixel according to a fifteenthembodiment.

FIG. 54 is a schematic cross-sectional view of the pixel of FIG. 53.

FIG. 55A schematically illustrates the pixel of FIG. 53 with nohorizontal electric field being produced.

FIG. 55B schematically illustrates the pixel of FIG. 53 with ahorizontal electric field being produced.

FIG. 56 is a plan view of an implementation in which a gate driver isconnected according to Variation 1.

FIG. 57 is a plan view of an implementation in which a gate driver isconnected according to Variation 2.

FIG. 58 is a plan view of pixel regions according to Variation 3.

FIG. 59 is a plan view of an implementation in which a gate driver isconnected according to Variation 4.

FIG. 60A is a plan view showing how lines may be arranged for the VAmode.

FIG. 60B is a plan view showing how lines may be arranged for the FFSmode.

FIG. 60C is a plan view showing how lines may be arranged for the IPSmode.

FIG. 61A is a schematic view of a display panel according to Variation6.

FIG. 61B is a schematic view of a tiled panel according to Variation 6.

FIG. 62 shows an example equivalent circuit of a gate driver accordingto Variation 7.

FIG. 63A is a plan view of pixel regions in which a TFT-A is provided.

FIG. 63B illustrates noise produced in a gate line due to a parasiticcapacitance between a netA and a source line.

FIG. 64A illustrates an example of a pattern of polarities where noiseis produced by a parasitic capacitance between a netA and a source line.

FIG. 64B illustrates an example of a pattern of polarities where noiseis produced by a parasitic capacitance between a netA and a source line.

FIG. 64C illustrates an example of a pattern of polarities where noiseis produced by a parasitic capacitance between a netA and a source line.

FIG. 65 is a waveform diagram for an implementation using the gatedrivers of Variation 7.

FIG. 66 is a plan view of an implementation in which the capacitor Cabof Variation 7 is connected.

FIG. 67 shows an equivalent circuit of a pixel according to Variation10.

FIG. 68A shows an equivalent circuit of an EL driver for controlling thepotential of a light-emission control line of Variation 10.

FIG. 68B is a timing chart illustrating how a gate line and alight-emission control line of Variation 10 are driven.

FIG. 69A is a schematic diagram of pixels in which gate drivers and ELdrivers are provided according to Variation 10.

FIG. 69B is a schematic diagram of pixels in which gate drivers and ELdrivers are provided according to Variation 10.

FIG. 69C is a schematic diagram of pixels in which gate drivers and ELdrivers are provided according to Variation 10.

FIG. 69D is a schematic diagram of pixels in which gate drivers and ELdrivers are provided according to Variation 10.

FIG. 69E is a schematic diagram of pixels in which gate drivers and ELdrivers are provided according to Variation 10.

FIG. 70 is a timing chart illustrating how the pixel of FIG. 67 isdriven.

FIG. 71 illustrates an example construction of an active-matrixsubstrate according to Variation 11.

FIG. 72 is a schematic diagram of an active-matrix substrate accordingto Variation 12.

FIG. 73A shows an equivalent circuit of gate drivers llx shown in FIG.72.

FIG. 73B shows an equivalent circuit of gate drivers lly shown in FIG.72.

FIG. 74 is a simplified schematic view of some pixel regions in which agate driver lly shown in FIG. 73B is provided.

FIG. 75A is a schematic view of pixel regions in which gate drivers llyare provided.

FIG. 75B is an enlarged schematic view of the portion defined by thebroken circle of FIG. 75A.

FIG. 76A is a schematic view of pixel regions in which gate drivers llyshown in FIG. 75A are provided.

FIG. 76B is an enlarged schematic view of the portion defined by thebroken ellipse of FIG. 76A.

FIG. 77 is a schematic diagram of an implementation in which gatedrivers 11 x(n) are arranged.

FIG. 78A illustrates an example of a pixel of Variation 14.

FIG. 78B schematically illustrates an implementation in which a line15L1 of Variation 14 is disposed.

FIG. 78C schematically illustrates an implementation in which a line15L1 of Variation 14 is disposed.

FIG. 79A schematically illustrates an implementation in which a line15L1 of Variation 14 is disposed.

FIG. 79B schematically illustrates an implementation in which a line15L1 of Variation 14 is disposed.

FIG. 80 is a schematic view of auxiliary capacitance electrodes and anauxiliary capacitance line according to Variation 15.

FIG. 81A is a schematic diagram of a pixel according to ExampleArrangement 1 of Variation 15.

FIG. 81B is a cross-sectional view of the pixel PIX of FIG. 81A takenalong line A-A.

FIG. 82A is a schematic diagram of a pixel according to ExampleArrangement 2 of Variation 15.

FIG. 82B is a cross-sectional view of the pixel PIX of FIG. 82A takenalong line B-B.

FIG. 83A is a schematic diagram of a pixel according to ExampleArrangement 3 of Variation 15.

FIG. 83B is a cross-sectional view of the pixel PIX of FIG. 83A takenalong line C-C.

FIG. 83C is a cross-sectional view of the pixel PIX of FIG. 83A takenalong line C-C.

EMBODIMENTS FOR CARRYING OUT THE INVENTION

An active-matrix substrate according to an embodiment of the presentinvention includes: a plurality of data lines; a plurality of linescrossing the plurality of data lines and including at least gate lines;and a driving circuit connected with at least one of the plurality oflines for controlling a potential of this line in response to a controlsignal supplied from outside a display region that includes pixelregions defined by the data lines and the gate lines, the drivingcircuit including a plurality of switching elements, at least one of theplurality of switching elements being located in one of the pixelregions (first arrangement).

In the first arrangement, the line to which the driving circuit isconnected may be a gate line or a line of another kind. The potential ofat least one of the lines crossing the data lines is controlled by thedriving circuit in response to a control signal supplied from outsidethe display region. At least one of the switching elements constitutinga part of the driving circuit is located inside a pixel region. Thus,compared with implementations where the potential of a line iscontrolled by an element at one end of the line, the present arrangementreduces dullness of a potential at the distal end of a line, therebydriving the line at high speed. Further, since at least one switchingelement of the driving circuit is located inside a pixel region, thepicture frame width may be made smaller than in implementations whereall the switching elements of the driving circuit are located outsidethe region of pixels.

In a second arrangement, starting from the first arrangement, thedriving circuit is connected with one of the gate lines and controls thepotential of this gate line by applying one of a selection voltage and anon-selection voltage to the gate line in response to the controlsignal.

In the second arrangement, one of a selection voltage and anon-selection voltage is applied to a gate line by a driving circuithaving at least one switching element located inside a pixel region.This reduces dullness of a potential of a gate line near its end,enabling switching the gate line between a selection state and anon-selection state at high speed. Further, at least one of theswitching elements of the driving circuit that controls the potential ofa gate line is located inside a pixel region, the picture frame widthmay be made smaller than in implementations where the driving circuit islocated outside the region of pixels.

A third arrangement, starting from the first or second arrangement,further includes: a first terminal located outside the display regionfor supplying a data signal to one of the plurality of data lines; and asecond terminal located outside the display region for supplying thecontrol signal to the driving circuit, the first and second terminalsbeing located outside a side of the display region that is parallel tothe gate lines.

In the third arrangement, a first terminal and a second terminal areprovided outside a side of the display region that is parallel to thegate lines. Thus, a data signal and a control signal can be supplied toa data line and the driving circuit, respectively, in the display regionfrom outside a side of the display region that is parallel to the gatelines, making it possible to reduce the width of the portions of thepicture frame along the other sides of the display region.

A fourth arrangement further includes: a pixel electrode located in oneof the pixel regions of the second or third arrangement and connectedwith one of the gate lines and one of the data lines, wherein a shieldlayer made of transparent conductive film is provided between one of theswitching elements of the driving circuit that is located in the pixelregion, and the pixel electrode. The fourth arrangement reducesinterference between the pixel electrode provided in a pixel region anda switching element of the driving circuit.

A fifth arrangement further includes a pixel electrode located in one ofthe pixel regions of the second or third arrangement and connected withone of the gate lines and one of the data lines, wherein one of theswitching elements of the driving circuit that is located in the pixelregion is disposed so as not to overlie the pixel electrode. The fiftharrangement reduces interference between the pixel electrode provided ina pixel region and the switching element of the driving circuit.

In a sixth arrangement, starting from one of the second to fiftharrangements, an adjustment line is further provided in a pixel regionin which the switching element of the driving circuit is not providedsuch that this pixel region has an aperture ratio substantially equal tothat of a pixel region in which a switching element of the drivingcircuit is provided. The sixth arrangement reduces the differencebetween the aperture ratio of the pixel regions with switching elementsof driving circuits and the aperture ratio of the pixel regions withoutsuch switching elements. This reduces luminance unevenness caused by thedifferent between the aperture ratio of the pixel regions with switchingelements of driving circuits and the aperture ratio of the pixel regionswithout such switching elements.

A seventh arrangement, starting from one of the third to sixtharrangements, further includes: a first insulating layer located betweena gate line layer forming the gate lines and a data line layer formingthe data lines; a control signal line located in one of the pixelregions and disposed in the data line layer so as to be generallyparallel to the data lines for supplying the control signal from thesecond terminal to the driving circuit; a second insulating layer havinga greater thickness than the first insulating layer and provided on topof the data line layer and including a contact hole extendingtherethrough to the data line layer; and a conductive layer portionprovided in the contact hole, wherein the control signal line isinterrupted at a location overlying one of the gate lines and portionsof the control line on this interruption are connected via theconductive layer portion in the contact hole of the second insulatinglayer.

In the seventh arrangement, a second insulating layer having a greaterthickness than the first insulating layer is provided on top of the dataline layer forming the control signal lines. The control signal line isinterrupted at a position where it overlies a gate line, with the firstinsulating layer being present in between, and the line portions acrossthe interruption are connected via a conductive layer portion in acontact hole provided in the second insulating layer. If a controlsignal line is provided above the gate lines, with the first insulatinglayer being present in between, then, a parasitic capacitance between agate line and a control signal line may cause a delay or disturbance ina control signal. In the present arrangement, the control signal line isnot present at locations that overlie the gate lines, and the portionsof the control signal line on the interruption are connected via acontact hole provided in the second insulating layer. Thus, a controlsignal line is more distant from the gate line than in implementationswhere a control signal line is located to overlie the gate line, therebyreducing the likelihood that a delay or disturbance occurs in a controlsignal caused by a parasitic capacitance between the gate line andcontrol signal line.

An eighth arrangement, starting from one of the third to sixtharrangements, further includes: a control signal line located in one ofthe pixel regions for supplying the control signal from the secondterminal to the driving circuit, wherein at least a portion of thecontrol signal line is disposed to be generally parallel to the datalines and located at generally the same distance from two data lines inthe pixel region. In the eighth arrangement, at least a portion of thecontrol signal line located in the pixel region is disposed to begenerally parallel to the data lines at a position where it is locatedat generally the same distance from the two data lines in the pixelregion. This reduces noise produced in a data line by the control signalline compared with implementations where a control signal line isdisposed close to a data line.

A ninth arrangement, starting from one of the second to eightharrangements, further includes: a pixel switching element located in oneof the pixel regions and connected with one of the data lines and one ofthe gate lines, wherein the gate line has portions with a width smallerthan the maximum width of the gate line, one of these portions beinglocated between the point on the gate line to which a gate terminal ofthe pixel switching element is connected and the intersection of thedata line and the gate line, and the other one of the portions beinglocated near the intersection of a portion of the gate line to which thegate terminal is not connected and the gate line.

In the ninth arrangement, the gate line has portions with a widthsmaller than the maximum width of the gate line, one of these portionsbeing located between its connection with the gate terminal of the pixelswitching element and its intersection with the data line, and the otherone of the portions being located near the intersection of a portion ofthe gate line to which the gate terminal is not connected and the dataline. Thus, the portion of the gate line that has a smaller width thanthe maximum width can be broken more easily than other portions. Whenthere is a short circuit near the intersection of a gate line and a dataline, the portion of the gate line with a smaller width than the maximumwidth may be broken to cut off the short-circuited portion, therebyallowing the data line and the pixel switching element to continue tofunction.

In a tenth arrangement, starting from one of the second to nintharrangements, each of the pixel regions corresponds to one of aplurality of colors, and the driving circuit is provided in a pixelregion corresponding to one of the plurality of colors. In the tentharrangement, a pixel region corresponds to one of a plurality of colors.The switching element of a driving circuit is provided in a pixel regioncorresponding to one of the colors. When a color filter is placed on thecounter-substrate, pixel regions are positioned in the locations thatcorrespond to the color filters of one color. For example, positioningthe switching element of a drive circuit in a pixel region thatcorresponds to a color that is less susceptible to luminance will reducecolor irregularity or the like caused by the difference between theaperture ratio of a pixel region with a switching element and that ofother pixel regions.

In an eleventh arrangement, a pixel region in which a switching elementof the driving circuit of one of the second to tenth arrangements isprovided has a larger dimension measured in a direction in which thegate lines extend than other pixel regions. In the eleventh arrangement,the aperture ratio of a pixel region with a switching element of adriving circuit and that for other pixel regions are substantially thesame such that the luminance for the entire display screen is uniform.

In a twelfth arrangement, the pixel region of one of the eighth toeleventh arrangements includes a pixel electrode connected with one ofthe gate lines and one of the data lines; and an auxiliary capacitanceelectrode connected with the pixel electrode, and the arrangementincludes: an auxiliary capacitance line located outside the displayregion and connected with the auxiliary capacitance electrode forsupplying a predetermined potential to the auxiliary capacitanceelectrode; and a low-impedance line located in the pixel region andconnected with the auxiliary capacitance electrode and connected withthe auxiliary capacitance line. The twelfth arrangement includes alow-impedance line connected with an auxiliary capacitance lineconnected, outside the display region, with an auxiliary capacitanceelectrode connected with a pixel electrode, and connected with theauxiliary capacitance electrode in the pixel region. Thus, even when theauxiliary capacitance electrode in the pixel region is affected by noisefrom a control signal line disposed in a pixel region and the potentialof the auxiliary capacitance line becomes different from a predeterminedlevel of potential supplied by the auxiliary capacitance line, thelow-impedance line may be used to return the potential to thepredetermined level.

In a thirteenth arrangement, starting from the second or thirdarrangement, a plurality of driving circuits are provided, each for oneof the gate lines. In the thirteenth arrangement, a plurality of drivingcircuits are provided, each for one of the gate lines. Thus, the gateline may be switched to a selection state at a higher speed than inimplementations where a single driving circuit is provided for one gateline.

In a fourteenth arrangement, starting from one of the second tothirteenth arrangements, the display region is divided into a pluralityof sub-regions arranged in a direction in which the gate lines arearranged, and a driving circuit provided for a gate line disposed ineach of the plurality of sub-regions applies a selection voltage to thegate line at a frequency that is specified for the sub-region.

In the fourteenth arrangement, the driving circuits apply selectionvoltages to the gate lines at different frequencies for differentsub-regions. Thus, a selection voltage may be applied to a gate line ina sub-region depending on an image displayed in this sub-region.

In a fifteenth arrangement, starting from one of the third to thirteentharrangements, N gate lines (N is a natural number) are provided, Mdriving circuits (M is a natural number, M≧2), i.e. a first to Mthdriving circuits, are provided for each of the gate lines, the M drivingcircuits provided for the nth gate line (1≦n≦N) apply a selectionvoltage to the nth gate line in the order beginning with the firstdriving circuit and ending with the Mth driving circuit, the second oneof the M driving circuits to the Mth drive circuit apply the selectionvoltage to the nth gate line at a time point at which the precedingdriving circuit applies the selection voltage to the n+1th gate line,and the first terminal supplies the data line with a data signal for animage to be written to the pixel region defined by the nth gate line andthe data line at a time point at which the Mth driving circuit appliesthe selection voltage to the nth gate line.

In the fifteenth arrangement, M driving circuits are provided for eachgate line, and they apply a selection voltage to a gate line in theorder beginning with the first driving circuit and ending with the Mthdriving circuit. The second to Mth driving circuits apply a selectionvoltage to the nth gate line at a time point at which the precedingdrive circuit applies a selection voltage to the n+1 gate line. The datalines crossing the nth gate line are supplied with a data signal at atime point at which a selection voltage is applied to the nth gate line.That is, the nth gate line is switched to a selection state M times bythe M driving circuits. Thus, the nth gate line may be pre-chargedbefore the data lines crossing the nth gate line receive a data signalsuch that data is written at a higher speed.

In a sixteenth arrangement, starting from one of the second tothirteenth arrangements, the pixel region includes a plurality ofsub-pixel regions, the lines include the gate lines and sub-gate lines,one of the sub-pixel regions includes a pixel electrode connected withone of the gate lines and one of the data lines, the other one of thesub-pixel regions includes a pixel electrode connected with one of thesub-gate lines and the data line and a capacitor connected between thispixel electrode and the pixel electrode in the one of the sub-pixelregions, the driving circuit includes a sub-gate line driver located ina pixel region in which the switching element is not provided, andprovided for one of the sub-gate lines for applying one of the selectionvoltage and the non-selection voltage to the sub-gate line in responseto the control signal, and the sub-gate line driver applies theselection voltage to the sub-gate line in one horizontal interval afterthe selection voltage is applied to the gate line.

In the sixteenth arrangement, when the selection voltage is applied tothe gate line in one horizontal interval, a voltage depending on a datasignal supplied to the source line is applied to the pixel electrode inthe one sub-pixel region. When the non-selection voltage is applied tothe gate line, the potential of the one sub-pixel region is in afloating state. Then, a selection voltage is applied by the sub-gateline driver to the sub-gate line, and a voltage depending on the datasignal is applied to the pixel electrode in the other sub-pixel region.This amplifies the potential of one of the sub-pixel regions through acapacitor. As a result, one sub-pixel region has a higher luminance indisplay than the other sub-pixel region. Further, the sub-gate linedriver is provided in the pixel region, reducing the picture frame widththan implementations where a sub-gate line driver is provided outsidethe display region.

In a seventeenth arrangement, starting from one of the second tothirteenth arrangements, the pixel region includes a plurality ofsub-pixel regions, the lines include the gate lines, sub-gate lines andauxiliary capacitance lines, the plurality of sub-pixel regions eachinclude a pixel electrode connected with one of the gate lines and oneof the data lines, one of the sub-pixel regions includes an auxiliarycapacitance connected with one of the auxiliary capacitance lines, and aswitching element including a gate terminal connected with one of thesub-gate lines, a source terminal connected with the pixel electrode inthe one of the sub-pixel regions, and a drain terminal connected withthe auxiliary capacitance, the driving circuit includes a sub-gate linedriver located in a pixel region in which the switching element is notprovided, and provided for one of the sub-gate lines for applying one ofthe selection voltage and the non-selection voltages to the sub-gateline, and the sub-gate line driver applies the selection voltage to thesub-gate line in response to the control signal after the selectionvoltage is applied to the gate line.

In the seventeenth arrangement, when the selection voltage is applied tothe gate line, the voltage depending on the data signal supplied to thedata line is applied to the pixel electrode in each of the sub-pixelregions. When the selection voltage is applied by the sub-gate linedriver to the sub-gate line after the selection voltage is applied tothe gate line, the charge in the auxiliary capacitance in one of thesub-pixel region is re-distributed among the pixel electrodes via theswitching element. Thus, the other one of the sub-pixel regions has apixel potential depending on the voltage of the data signal, and the oneof the sub-pixel regions goes to the pixel potential that depends on thevoltage of the data signal and then the potential increases or decreasesdepending on the potential of the auxiliary capacitance line. Thisallows an image to be displayed with different pixel potentials in theone and the other one of the sub-pixel regions, and thus with differentlevels of luminance within one pixel region. Further, since the sub-gateline driver is provided inside a pixel region, the picture frame widthmay be reduced compared with that in implementations where a sub-gateline driver is provided outside the display region.

In an eighteenth arrangement, starting from one of the second tothirteenth arrangements, the pixel region includes a plurality ofsub-pixel regions, the lines include the gate lines, first auxiliarycapacitance lines and second auxiliary capacitance lines, the pluralityof sub-pixel regions each include a pixel electrode connected with oneof the gate lines and one of the data lines, one of the sub-pixelregions includes a first auxiliary capacitance connected with the pixelelectrode in the one of the sub-pixel region and one of the firstauxiliary capacitance lines, the other one of the sub-pixel regionsincludes a second auxiliary capacitance connected with the pixelelectrode in the other one of the sub-pixel regions and one of thesecond auxiliary capacitance line, the driving circuit includes anauxiliary capacitance line control element provided inside the displayregion for controlling a potential of the first auxiliary capacitanceline and a potential of the second auxiliary capacitance line, and theauxiliary capacitance line control element applies voltages to the firstauxiliary capacitance line and the second auxiliary capacitance linesuch that the potential of the first auxiliary capacitance line and thepotential of the second auxiliary capacitance line have opposite phasesafter the selection voltage is applied to the gate line.

In the eighteenth arrangement, voltages are applied to the first andsecond auxiliary capacitance lines such that the potentials of the firstand second auxiliary capacitance lines are made to have opposite phasesby the auxiliary capacitance control element after one horizontalinterval of the gate lines ends. In one horizontal interval of the gatelines, the potential of the data lines is applied to the pixel electrodeof one sub-pixel region and the pixel electrode of the other sub-pixelregion. After the selection voltage is applied to the gate line, thecharges held in the first and second auxiliary capacitances increase ordecrease depending on the potentials of the first and second auxiliarycapacitance lines. Thus, one sub-pixel region may have a higher pixelpotential than the other sub-pixel region and thus can display an imageat a higher luminance than the other sub-pixel region. Further, sincethe auxiliary capacitance control element is provided inside the regionof pixels, the picture frame width may be reduced compared with that inimplementations where an auxiliary capacitance control element isprovided outside the display region.

In a nineteenth arrangement, starting from one of the second tothirteenth arrangements, the lines include the gate lines and auxiliarycapacitance lines, the pixel region includes a pixel electrode connectedwith one of the gate lines and one of the data lines and an auxiliarycapacitance connected with the pixel electrode and one of the auxiliarycapacitance lines, the driving circuit includes auxiliary capacitanceline drivers each provided for one of the auxiliary capacitance lines,and the auxiliary capacitance line driver applies a voltage with thesame polarity as the voltage on the data line to the auxiliarycapacitance line in response to the control signal.

In the nineteenth arrangement, the auxiliary capacitance line driverapplies to the auxiliary capacitance line a voltage with the samepolarity as that for the data line. The potential of the pixel electrodechanges through the auxiliary capacitance depending on the potential ofthe auxiliary capacitance line. Accordingly, when the data line has apositive potential, a positive voltage is applied to the auxiliarycapacitance line. Then, the pixel electrode has a potential that dependson the data line, and the potential increases through the auxiliarypotential. This reduces the amplitude of the data signal applied to thepixel electrode compared with implementations without the presentarrangement, thereby reducing power consumption. Further, since theauxiliary capacitance line driver is provided inside the region ofpixels, the picture frame width may be made smaller than inimplementation where an auxiliary capacitance line driver is providedoutside the display region.

In a twentieth arrangement, starting from one of the second to nintharrangements, the driving circuit is provided in each of K regions (K isa natural number, K≧2) arranged in a direction in which the gate linesof the display region extend, each driving circuit being provided forevery K gate lines, driving circuits being provided on different gatelines in different regions. In the twentieth arrangement, a drivingcircuit is provided in each of K regions arranged in a direction inwhich the gate lines extend in the display region, each driving circuitbeing provided for every K gate lines. Driving circuits are provided ondifferent gate lines in different regions. Thus, within one region, thenumber of pixel regions without a driving circuit is larger than inimplementations where a driving circuit is provided for every gate line,thereby improving the aperture ratio.

In a twenty-first arrangement, starting from the twentieth arrangement,the pixel region corresponds to one of a plurality of colors, and thedriving circuit is provided in the pixel region corresponding to one ofthe plurality of colors. In the twenty-first arrangement, the switchingelement of a driving circuit is provided in the pixel region for oneparticular color. Thus, for example, positioning the switching elementof a drive circuit in a pixel region that corresponds to a color that isless susceptible to luminance will reduce color irregularity or the likecaused by the difference between the aperture ratio of a pixel regionwith a switching element and that of other pixel regions.

In a twenty-second arrangement, starting from the twenty-firstarrangement, a pixel region in which a switching element of the drivingcircuit is provided has a larger dimension measured in a direction inwhich at least one of the gate line and the data line extend than otherpixel regions. In the twenty-second arrangement, a pixel region in whicha switching element of the driving circuit is provided has a largerdimension measured in a direction in which at least one of the gate lineand the data line extends than other pixel regions. This reduces thedecrease in the aperture ratio of a pixel region with a switchingelement of a driving circuit such that the aperture ratio in the displayregion is uniform.

In a twenty-third arrangement, starting from one of the second tothirteenth arrangements, the lines include the gate lines and commonelectrode lines, the pixel region includes a pixel electrode connectedwith one of the gate lines and one of the data lines and an auxiliarycapacitance connected with the pixel electrode and one of the commonelectrode lines, the driving circuit includes common electrode driverseach located in a pixel region in which the switching element is notprovided, and provided for one of the common electrode lines, and thecommon electrode driver applies to the common electrode line a voltagewith a polarity opposite that of the potential of the data line inresponse to the control signal.

In the twenty-third arrangement, a voltage with a polarity opposite thatof the potential of the data lines is applied by the common electrodedriver to a common electrode line. The potential of a pixel electrodechanges through an auxiliary capacitance depending on the potential ofthe common electrode line. Since the potentials of the data lines andthe common electrode lines have opposite polarities, the amplitude of adata signal supplied to the data line may be reduced, thereby reducingpower consumption. Further, since the common electrode driver isprovided inside the region of pixels, the picture frame width may bemade smaller than in implementation where a common electrode driver isprovided outside the display region.

In a twenty-fourth arrangement, starting from one of the first to fourtharrangements, the lines include the gate lines and light-emissioncontrol lines, the pixel region includes a light-emitting element, anelectric circuit connected with one of the data lines and one of thegate lines, and a light-emission control switching element having a gateterminal connected with one of the light-emission control lines, asource terminal connected with the electric circuit, and a drainterminal connected with the light-emitting element, the driving circuitincludes light-emission control line drivers each provided for one ofthe light-emission control lines for controlling a potential of thelight-emission control line in response to the control signal.

In the twenty-fourth arrangement, the light-emission control line drivercontrols the potential of the light-emission control line. Thelight-emission control switching element has a gate terminal connectedwith a light-emission control line and is connected between thelight-emitting element and the electric circuit. This enables switchingthe connection of the light-emitting element and electric circuitdepending on the potential of the light-emission control line, therebycontrolling light emission.

A display panel according to an embodiment of the present inventionincludes: the active-matrix substrate of one of the first totwenty-second arrangements; a counter-substrate having a color filterand a counter-electrode; and a liquid crystal layer sandwiched betweenthe active-matrix substrate and the counter-substrate (twenty-fiftharrangement).

A display panel according to an embodiment of the present inventionincludes: the active-matrix substrate of the twenty-third arrangement; acounter-substrate having a color filter; and a liquid crystal layersandwiched between the active-matrix substrate and the counter-substrate(twenty-sixth arrangement).

In the twenty-fifth or twenty sixth arrangement, at least one of thedriving circuits is provided inside the region of pixels, reducingdullness of a signal in a signal line compared with implementationswhere a signal is input at one end of the signal line, allowing an imageto be displayed appropriately.

In a twenty-seventh arrangement, at least one element of the drivingcircuit is provided on the active-matrix substrate of the display panelof the twenty-fifth or twenty sixth arrangement in a dark-line regionthat is produced depending on orientation in the liquid crystal layerwithin the pixel region. Light transmission is smaller in a dark-lineregion produced depending on the orientation in the liquid crystal layerof the pixel region. The twenty-seventh arrangement provides a drivingcircuit in a dark-line region, thereby reducing the decrease in thelight transmission caused by driving circuits provided in the pixelregion.

A display device according to an embodiment of the present inventionincludes: the display panel of one of the twenty-fifth to twenty-seventharrangements; and a housing containing the display panel, the housingincluding a first cover portion located to overlie a portion of apicture frame region of the display panel and a portion of the displayregion and having a lens with a viewer's side that is curved in shape,and a second cover portion covering at least a side of the display panel(twenty-eighth arrangement). In the twenty-eighth arrangement, the lenslocated to overlie the picture frame region of the display panel causeslight emitted from the display surface to be refracted before advancingtoward the viewer such that the picture frame region is unlikely to bevisible to the viewer.

Embodiments of the present invention will be described below in detailwith reference to the drawings. The same or corresponding components inthe drawings are labeled with the same reference numerals and theirdescription will not be repeated.

First Embodiment

(Construction of Liquid Crystal Display Device)

FIG. 1 is a schematic plan view of a liquid crystal display deviceaccording to the present embodiment. The liquid crystal display device 1includes a display panel 2, a source device 3, a display control circuit4, and a power supply 5. The display panel 2 includes an active-matrixsubstrate 20 a, a counter-substrate 20 b, and a liquid crystal layer(not shown) sandwiched between these substrates. Although not shown inFIG. 1, a polarizer is provided on the lower side of the active-matrixsubstrate 20 a and another polarizer is provided on the upper side ofthe counter-substrate 20 b. On the counter-substrate 20 b are provided:a black matrix, red (R), green (G) and blue (B) color filters, and acommon electrode (all not shown).

As shown in FIG. 1, the active-matrix substrate 20 a is electricallyconnected with the source driver 3, which is provided on a flexiblesubstrate. The display control circuit 4 is electrically connected withthe display panel 2, source driver 3 and power supply 5. The displaycontrol circuit 4 provides control signals to the source driver 3 anddriving circuits, described below, provided on the active-matrixsubstrate 20a (hereinafter referred to as gate drivers). Examples ofcontrol signals include reset signals (CLR) for displaying an image onthe display panel 2, clock signals (CKA, CKB) and data signals. Thepower supply 5 is electrically connected with the display panel 2,source driver 3 and display control circuit 4 for supplying power supplyvoltage signals thereto.

(Construction of Active-Matrix Substrate)

FIG. 2 is a schematic plan view of the active-matrix substrate 20 a. Onthe active-matrix substrate 20 a are provided a plurality of gate lines13G extending from one end to the other end of the substrate disposed inthe X-direction, separated at a constant distance and substantiallyparallel to each other. Further, a plurality of source lines 15S (datalines) are provided on the active-matrix substrate 20 a to cross thegate lines 13G. The region defined by a gate line 13G and source line15S forms one pixel. Each pixel corresponds to one of the colors of thecolor filters.

FIG. 3 is a schematic plan view of the active-matrix substrate 20 awithout the source lines 15S and components connected with theactive-matrix substrate 20 a. As shown in the implementation of FIG. 3,each gate driver 11 (i.e. driving circuit) is provided between a gateline 13G and another gate line 13G in the display region. In the presentimplementation, four gate drivers 11 are connected with each gate line13G. Terminals 12 g (i.e. second terminals) are provided in the portionof the picture frame region along that side of the display region of theactive-matrix substrate 20 a that the source device 3 adjoins. Theterminals 12 g are connected with the control circuit 4 and power supply5. The terminals 12 g receive signals such as control signals (CKA, CKB)and power supply voltage signals provided by the control circuit 4 andpower supply 5. The signals such as control signals (CKA, CKB) and powersupply voltage signals supplied to the terminals 12 g are supplied tothe gate drivers 11 via the lines 15L1. Each gate driver 11, in responseto a supplied signal, provides a voltage signal indicating one of theselection state and non-selection state to the gate line 13G to which itis connected, and provides the same voltage signal to the gate driver ofthe subsequent row. In the following description, a voltage signalcorresponding to the selection state or non-selection state will besometimes referred to as scan signal. And the state of a gate line 13Gbeing selected will be referred to as driving of the gate line 13G.

Further, terminals 12 s (i.e. first terminals) connecting the sourcedriver 3 with the source lines 15S are provided on the portions of thepicture frame region of the active-matrix substrate 20 a that arelocated along the side thereof that the source device 3 adjoins. Inresponse to control signals supplied by the display control circuit 4,the source drivers 3 provide data signals to the source lines 15S.

As shown in FIG. 3, in the present embodiment, in the display region, aplurality of gate drivers 11 are connected with each of the gate lines13G: GL(1) to GL(n). The gate drivers 11 connected with one and the samegate line 13G are synchronized, and scan signals provided by these gatedrivers 11 simultaneously drive one gate line 13G. In the presentembodiment, a plurality of gate drivers 11 connected with one gate line13G are separated substantially by the same distance such that the loadon each of the gate drivers 11 driving a gate line 13G is substantiallythe same.

(Construction of Gate Driver)

The construction of the gate drivers 11 of the present embodiment willbe described below. FIG. 4 shows an example of an equivalent circuit ofa gate driver 11 located between gate lines 13G: GL(n−1) and GL(n−2) fordriving the gate line 13G: GL(n−1). As shown in FIG. 4, the gate driver11 includes a TFT-A to TFT-J constituted by thin-film transistors (TFT)that serve as switching elements, a capacitor Cbst, terminals 111 to120, and terminals for receiving low-level power supply voltage signals.

The terminals 111 and 112 each receive a set signal (S) via the the gateline 13G of the preceding row GL(n−2). The terminals 111 and 112 of agate driver 11 connected with the gate line 13G: GL(1) each receive agate start pulse signal (S) provided by the display control circuit 4.The terminals 113 to 115 each receive a reset signal (CLR) provided bythe display control circuit 4. The terminals 116 and 117 each receive aclock signal (CKA) supplied. The terminals 118 and 119 each receive aclock signal (CKB) supplied. The terminal 120 provides a set signal(OUT) to the gate line 13G of the subsequent row.

The clock signal (CKA) and clock signal (CKB) are two-phase clocksignals whose phase is reversed at each horizontal scan interval (seeFIG. 9). FIG. 4 shows a gate driver 11 for driving the gate line 13G:GL(n−1); in a gate driver 11 of the subsequent row for driving the lineGL(n), the terminals 116 and 117 each receive a clock signal (CKB), andthe terminals 118 and 119 of this gate driver 11 each receive a clocksignal (CKA). That is, the terminals 116 and 117 and terminals 118 and119 of a given gate driver 11 receive clock signals of the phaseopposite that of clock signals received by the gate drivers 11 of theadjacent lines.

In FIG. 4, the line to which the source terminal of the TFT-B, the drainterminal of the TFT-A, the source terminal of the TFT-C, one of theelectrodes of the capacitor Cbst and the gate terminal of the TFT-F areconnected will be referred to as “netA”. The line to which the gateterminal of the TFT-C, the source terminal of the TFT-G, the drainterminal of the TFT-H, the source terminal of the TFT-I and the sourceterminal of the TFT-J are connected will be referred to as “netB”.

The TFT-A is composed of two TFTs (A1, A2) connected in series. The gateterminals of the TFT-A are connected with the terminal 113, the drainterminal of A1 is connected with the netA, the source terminal of theelement A2 is connected with the power supply voltage terminal VSS.

The TFT-B is composed of two TFTs (B1, B2) connected in series. The gateterminals of the TFT-B and the drain terminal of the element B1 areconnected with the terminal 111 (which constitutes a diode connection),and the source terminal of the element B2 is connected with the netA.

The TFT-C is composed of two TFTs (C1, C2) connected in series. The gateterminals of the TFT-C are connected with the netB, the drain terminalof the element C1 is connected with the netA, and the source terminal ofthe element C2 is connected with the power supply voltage terminal VSS.

The capacitor Cbst has one electrode connected with the netA and theother electrode connected with the terminal 120.

The TFT-D has a gate terminal connected with the terminal 118, a drainterminal connected with the terminal 120 and a source terminal connectedwith the power supply voltage terminal VSS.

The TFT-E has a gate terminal connected with the terminal 114, a drainterminal connected with the terminal 120 and a source terminal connectedwith the power supply voltage terminal VSS.

The TFT-F has a gate terminal connected with the netA, a drain terminalconnected with the terminal 116 and a source terminal connected with theoutput terminal 120.

The TFT-G is composed of two TFTs (G1, G2) connected in series. The gateterminals of the TFT-G and the drain terminal of G1 are connected withthe terminal 119 (which constitutes a diode connection), and the sourceterminal of G2 is connected with the netB.

The TFT-H has a gate terminal connected with the terminal 117, a drainterminal connected with the netB and source terminal connected with thepower supply voltage terminal VSS.

The TFT-I has a gate terminal connected with the terminal 115, a drainterminal connected with the netB and a source terminal connected withthe power supply voltage terminal VSS.

The TFT-J has a gate terminal connected with the terminal 112, a drainterminal connected with the netB and a source terminal connected withthe power supply voltage terminal VSS.

FIG. 4 shows an example where the TFT-A, B, C and G each is composed oftwo TFTs connected in series; alternatively, each of them may becomposed of one TFT.

(Overall Layout of Gate Drivers)

Now, how various elements of gate drivers 11 are disposed in the displayregion will be described. FIGS. 5A to 5C show how one gate driver 11located between the rows GL(n) and GL(n−1) and another one locatedbetween the rows GL(n−1) and GL(n−2) may be disposed. For convenience,FIGS. 5A to 5C show the pixel regions 211R to 217B between the rowsGL(n) and GL(n−1) separated from the pixel regions 201R to 207B betweenthe rows GL(n−1) and GL(n−2); in reality, the rows of pixel regionsoverlap each other at the gate line 13G: GL(n−1) and the upper row ofpixel regions and the lower row of pixel regions are continuous. R, Gand B contained in reference characters indicating pixel regions eachindicate the color of a color filter (not shown) provided on thecounter-substrate 20 b.

As shown in FIG. 5A to 5C, in the row of pixel regions 211R to 217B(hereinafter referred to as upper pixel region row) and the row of pixelregions 201R to 207B (hereinafter referred to as lower pixel regionrow), TFTs for displaying an image (hereinafter referred to as TFT-PIX)(i.e. pixel switching elements) are each located near the intersectionof a source line 15S and gate line 13G.

In the upper and lower pixel region rows, a gate driver 11 is composedof distributed elements (i.e. one of the TFT-A to TFT-J and capacitorCbst). A pixel region that includes a switching element (i.e. TFT-A, Cto F, H to J) that receives one of clock signals (CKA, CKB), a resetsignal (CLR) and a power supply voltage signal has a line 15L1 providedtherein for supplying such a signal. Lines 15L1 extend substantiallyparallel to the source lines 15S through the upper and lower pixelregion rows. Further, lines 13N for the netA and netB are provided inthe upper and lower pixel region rows. Each of the lines 13N extendsthrough the upper and lower pixel region rows and substantially parallelto the gate lines 13G and through pixel regions in which elementsconnected with the netA and netB (i.e. TFT-A to C, F, G to J, and Cbst)are disposed.

In the present embodiment, the TFTs are arranged such that the clocksignals supplied to the TFT-D, TFT-F, TFT-H and TFT-G of a gate driver11 have a phase opposite that of the clock signals supplied to such TFTsof a gate driver 11 in an adjacent row. That is, the TFT-D, TFT-F, TFT-Hand TFT-G are positioned in pixel regions that are horizontallydisplaced from the pixel regions in which such TFTs of an adjacent roware provided.

More specifically, as shown in FIG. 5A, the TFT-D of the upper pixelregion row is located in the pixel regions 211R and 211G while the TFT-Dof the lower pixel region row is located in the pixel regions 201B and202R. The TFT-F of the upper pixel region row is located in the pixelregion 213G while the TFT-F of the lower pixel region row is located inthe pixel region 203R. Further, as shown in FIG. 5C, the TFT-H of theupper pixel region row is located in the pixel regions 215G and 215Bwhile the TFT-H of the lower pixel region row is located in the pixelregions 206R and 206G. The TFT-G of the upper pixel region row islocated in the pixel region 216G while the TFT-G of the lower pixelregion row is located in the pixel region 205B. Thus, a clock signal(CKA) is supplied to the TFT-D of the upper pixel region row while aclock signal (CKB) with a phase opposite that of the clock signal (CKA)is supplied to the TFT-D of the lower pixel region row. The same appliesto the TFT-G and TFT-H: as shown in FIGS. 5A and 5C, a clock signal (CKAor CKB) of one phase is supplied to the upper pixel region row, while aclock signal of the opposite phase is supplied to the lower pixel regionrow.

Further, the TFT-B and TFT-J of the upper pixel region row are connectedwith the gate line 13G: GL(N−1) while the TFT-B and TFT-J of the lowerpixel region row are connected with the gate line 13G: GL(n−2). TheTFT-D and TFT-F of the upper pixel region row are connected with thegate line 13G: GL(n) while the TFT-D and TFT-F of the lower pixel regionrow are connected with the gate line 13G: GL(n−1). The gate driver 11located in the lower pixel region row receives a set signal (S) via thegate line 13G: GL(n−2) and, then, provides the set signal (S) to thegate line 13G: GL(n) and drives the gate line 13G: GL(n−1). The gatedriver 11 located in the upper pixel region row receives a set signal(S) via the gate line 13G: GL(n−1) and, then, provides the set signal(S) to the gate line 13G: GL(n+1) and drives the gate line 13G: GL(n).

How the elements constituting a gate driver 11 are connected will bedescribed below. FIG. 6 is an enlarged plan view of the pixel regions204G and 204B in which the TFT-A of FIG. 5B is provided. The TFT-A andTFT-H, I, and J are each constructed using two pixel regions and theirelements are connected in the same manner; accordingly, the TFT-A willbe described as an example. In FIG. 6, the region BM defined by two-dotchain lines is the region where light is blocked by a black matrix (notshown) provided on the counter-substrate 20b (hereinafter referred to aslight-shielding region BM). The light-shielding region BM includesregions where the gate lines 13G, the elements constituting the gatedriver 11 and the source lines 15S are located.

As shown in FIG. 6, a TFT-PIX for displaying an image is provided nearthe intersection of a gate line 13G and source line 15S. The TFT-PIX isconnected with a pixel electrode 17 via a contact CH1. Further, in eachpixel region, a line 15L1 is provided to extend substantially parallelto the source lines 15S and cross the gate lines 13G. A power supplyvoltage signal (VSS) is supplied to the line 15L1 in the pixel region204G, and a reset signal (CLR) is supplied to the line 15L1 of the pixelregion 204B.

As shown in FIG. 6, the gate terminal 13 g of the TFT-A is located inthe pixel regions 204B to 204G. The line 13N is provided in the pixelregions 204G and 204B to cross the source lines 15S and lines 15L1 andsubstantially parallel to the gate lines 13G. The line 13N constitutesthe netA and netB, described above. The TFT-A is connected with the line15L1 via the contact CH2 of the pixel region 204B and is connected withthe line 13N via the contact CH2 of the pixel region 204G. Further, inthe present embodiment, a shield layer 16 is provided between the pixelelectrodes 17 and TFT-A, lines 13N and 15L1.

FIG. 7A shows a cross-sectional view of a TFT-PIX of FIG. 6 taken alongline I-I, while FIG. 7B shows a cross-sectional view of the contact CH1taken along line II-II. Further, FIG. 7C shows a cross-sectional view ofthe TFT-A of FIG. 6 taken along line III-III, while FIG. 7D shows across-sectional view of the contact CH2 taken along line IV-IV.

As shown in FIGS. 7A, 7C and 7D, the gate line 13G, the gate terminal 13g of the TFT-A and the line 13N are formed as a gate line layer 13 isformed on the substrate 20. As shown in FIGS. 7A and 7C, a semiconductorlayer portion 14 formed of an oxide semiconductor is provided on top ofthe gate line layer 13, with a gate insulating film 21 being present inbetween, in the areas where a TFT-PIX is to be formed and a TFT-A is tobe formed. Further, above the substrate 20 which has the semiconductorlayer portion 14 provided thereon is provided a source line layer 15portions separated across the top of the semiconductor layer portion 14.Thus, as shown in FIGS. 7A to 7C, the source line 15S, the source-drainterminal 15SD of the TFT-PIX, the source-drain terminal 15sd (including15 sd 1 and 15 sd 2) of the TFT-A and line 15L1 are formed.

As shown in FIG. 7D, at the contact CH2 of the pixel region 204B, acontact hole H2 is formed in the gate insulating film 21 to extendthroughout to the surface of the gate layer 13. The source line layer 15(15L1) is provided on the gate insulating film 21 to contact the gateline layer 13(13 g) at the contact hole H2. Thus, the gate terminal 13 gof the TFT-A is connected with the line 15L1 at the contact CH2 of thepixel region 204B. Similarly, at the contact CH2 of the pixel region204G, the drain terminal 15 sd 1 of the element A1 of the TFT-A formedby the source line layer 15 is connected with the line 13N formed by thegate line layer 13. Thus, the TFT-A is connected with the netA, and areset signal (CLR) is supplied through the line 15L1.

Further, as shown in FIGS. 7A to 7D, on top of the source line layer 15are stacked a protection film 22 and protection film 23 to cover thesource line layer 15. The protection film 22 is formed of an inorganicinsulating film such as SiO2, for example. The protection film 23 isformed of an organic insulating film such as a positive photosensitiveresin film, for example. Further, as shown in FIGS. 7A and 7D, a shieldlayer 16 is provided on top of the protection film 23. The shield layer16 is formed of a transparent conductive film such as ITO, for example.Then, on top of the shield layer 16 is provided an interlayer insulatinglayer 24 formed of an inorganic insulating film such as SiO2, forexample. On top of the interlayer insulating layer 24 are provided pixelelectrodes 17 formed of a transparent conductive film such as ITO, asshown in FIGS. 7C and 7D.

As shown in FIG. 7B, at the contact CH1, a contact hole H1 is providedabove the drain terminal 15D of the TFT-PIX to extend through theinterlayer insulating layer 24, shield layer 16 and protection films 22and 23. The pixel electrode 17 is provided on top of the interlayerinsulating layer 24 to contact the drain terminal 15D in the contacthole H1. Forming the shield layer 16 forms a capacitance Cs between thepixel electrode 17 and shield layer 16, and the capacitance Csstabilizes the potential of the pixel electrode 17.

Thus, the TFT-A and the line 13N and lines 15L1 connected with the TFT-Aare located in two pixel regions, thereby reducing the decrease in theaperture ratio compared with implementations where they are located inone pixel region. Further, a shield layer 16 is provided between thepixel electrode 17 and the TFT-A, line 13N and lines 15L1, therebyreducing interference between the TFT-A or the like and the pixelelectrode 17.

(TFT-B)

How the TFT-B is connected will be described below. FIG. 8A is anenlarged plan view of the pixel region 204R of FIG. 5B. In FIG. 8A, thelight-shielding region BM is not shown. As shown in FIG. 8A, in thepixel region 204R, as is the case in the pixel region 204G describedabove, a TFT-PIX is connected with a pixel electrode 17 at the contactCH1. Further, the source-drain terminal 15 sd (including 15 sd 1 and 15sd 2) of the TFT-B are formed by the source line layer 15. The gateterminal 13 g of the TFT-B, the gate line 13G: GL(n−2) and line 13N areformed by the gate line layer 13.

The drain terminal 15 sd 1 of the element B1 crosses the gate line 13G:GL(n−2) and line 13N. At the contacts CH3 and CH4, as at the contact CH2described above, a contact hole H2 is formed in the gate insulating film21 for connecting the gate line layer 13 with the source line layer 15.

The drain terminal 15 sd 1 is connected with the gate line 13G: GL(n−2)via the contact CH3, and is connected with the gate terminal 13 g viathe contact CH4. The source terminal 15 sd 2 of the element B2 isconnected with the line 13N via the contact CH2. Thus, the TFT-B isconnected with the netA and receives a set signal (S) via the gate line13G: GL (n−2).

(TFT-C)

How the TFT-C is connected will be described below. FIG. 8B is anenlarged plan view of the pixel region 205R of FIG. 5B. In FIG. 8B, thelight-shielding region BM is not shown. As shown in FIG. 8B, in thepixel region 205R, as is the case in the pixel regions 204G and 204Bdescribed above, the TFT-PIX is connected with the pixel electrode 17via the contact CH1. Further, the gate terminal 13g of the TFT-C, thegate line 13G and line 13N (13Na, 13Nb) are formed by the gate linelayer 13. The source-drain terminal 15 sd (including 15 sd 1 and 15 sd2) of the TFT-C and line 15L1 are formed by the source line layer 15.The drain terminal 15 sd 1 of the element C1 is connected with the line13Na via the contact CH2. The TFT-C is connected with the netA via theline 13Na, and is connected with the netB via the line 13Nb. Further, apower supply voltage signal (VSS) is supplied to the TFT-C via the line15L1.

(TFT-F)

How the TFT-F is connected will be described below. FIG. 8C is anenlarged plan view of the pixel region 203R of FIG. 5A. In FIG. 8C, thelight-shielding region BM is not shown. As shown in FIG. 8C, in thepixel region 203R, as is the case in the pixel regions 204G and 204B,the TFT-PIX is connected with the pixel electrode 17 via the contactCH1. Further, the gate terminal 13 g of the TFT-F, the gate line 13G andline 13N are formed by the gate line layer 13. The source terminal 15 sand the drain terminal 15 d of the TFT-F, and line 15L1 are formed bythe source line layer 15.

At the contact CH5, as at the contact CH2 described above, a contacthole H2 is provided for connecting the gate line layer 13 with thesource line layer 15. The source terminal 15 s of the TFT-F is connectedwith the gate line 13G: GL(n−1) via the contact CH5, and the gateterminal of the TFT-F is connected with the netA. A clock signal (CKA)is supplied to the drain terminal 15 d of the TFT-F via the line 15L1.Further, the TFT-F provides a scan signal to the gate line 13G: GL(n−1)via the contact CH5.

(TFT-G)

How the TFT-G is connected will be described below. FIG. 8D is anenlarged plan view of the pixel region 205B of FIG. 5C. In FIG. 8D, thelight-shielding region BM is not shown. As shown in FIG. 8D, in thepixel region 205B, as is the case in the pixel regions 204G and 204B,the TFT-PIX is connected with the pixel electrode 17 via the contactCH1. Further, the gate terminal 13 g of the TFT-G, the gate line 13G andline 13N are formed by the gate line layer 13. The source-drain terminal15 sd (including 15 sd 1 and 15 sd 2) of the TFT-G and line 15L1 areformed by the source line layer 15. The source terminal 15 sd 2 of theelement G2 of the TFT-G is connected with the line 13N via the contactCH2. The gate terminal 13 g of the TFT-G is connected with the drainterminal 15 sd 1 of the element G1 and line 15L1 via the contact CH4.Thus, the TFT-G is connected with the netB, and a clock signal (CKB) issupplied thereto via the line 15L1.

(Cbst)

How the capacitor Cbst is connected will be described below. FIG. 8E isan enlarged plan view of the pixel region 203B of FIG. 5B. In FIG. 8E,the light-shielding region BM is not shown. In the pixel region 203B, asis the case in the pixel regions 204G and 204B described above, theTFT-PIX is connected with the pixel electrode 17 via the contact CH1.Further, one of the electrodes constituting the capacitor Cbst, 13 c,the gate line 13G and line 13N are formed by the gate line layer 13. Theother one of the electrodes of the capacitor Cbst, 15 c, the connection15Lc and line 15L2 are formed by the source line layer 15. As shown inFIG. 8E, the connection 15Lc has substantially the same width as theline 13N, extends from the electrode 15 c to the contact CH2 and isconnected with the line 13N via the contact CH2. The line 15L2 extendsfrom the end of the connection 15Lc adjacent the contact CH2 to thevicinity of the contact CH1. In the present embodiment, the line 15L2 isformed such that the aperture ratio of a pixel region with a capacitorCbst is equal to that of other pixel regions. At the contact CH2, theelectrode 15 c is connected with the line 13N via the contact 15Lc.Thus, the capacitor Cbst is connected with the netA.

(TFT-D, E)

How the TFT-D and TFT-E are connected will be described below. In theTFT-D and TFT-E, as is the case in the TFT-A described above, the gateterminal 13 g is located in two adjacent pixel regions, and the line15L1 in one of the pixel regions is connected with the gate terminal 13g. The TFT-D and TFT-E are only different in that the reset signal (CLR)or clock signal (CKA) is supplied to the respective gate terminal; thus,only how the TFT-D is connected will be described.

FIG. 8F is an enlarged plan view of the pixel regions 201B and 202R ofFIG. 5A. In FIG. 8F, the light-shielding region BM is not shown. In thepixel regions 201B and 202R, as is the case in the pixel regions 204Gand 204B described above, forming a source line layer 15 forms thesource terminal 15 s and drain terminal 15 d of the TFT-D and the line15L1. The drain terminal 15d is connected with the gate line 13G:GL(n−1) at the contact CH5 of the pixel region 201R. The power supplyvoltage signal (VSS) and clock signal (CKA) are supplied to the TFT-Dvia the lines 15L1 of the pixel regions 201B and 202R, and the TFT-Ddrives the gate line 13G: GL(n−1) via the contact CH5 and provides theset signal to the gate line 13G: GL(n).

The foregoing is an example of how the gate driver 11 is constructed andhow their elements are connected. The pixel regions in which the TFT-Bto TFT-E, TFT-F, TFT-G, capacitor Cbst and TFT-D are provided are notdescribed; in these pixel regions, as is the case in the pixel region inwhich the TFT-A is provided, a source line layer 15 is provided, and ontop of this are stacked protection films 22 and 23, a shield layer 16,an interlayer insulating film 24 and a pixel electrode 17.

(Operation of Gate Driver 11)

Now, the operation of a gate driver 11 will be described with referenceto FIGS. 4 and 9. FIG. 9 is a timing chart showing signals encounteredwhen the gate driver 11 scans a gate line 13G. In FIG. 9, the periodfrom t3 to t4 is the period in which the gate line 13G: GL(n) isselected. Clock signals (CKA) and (CKB), whose phase is reversed at eachhorizontal scan interval, are supplied from the display control circuit4 to the gate driver 11 via the terminals 116 to 119. Although not shownin FIG. 9, a reset signal (CLR) that goes to H (high) level at eachvertical scan interval and remains that way for a predetermined periodof time is supplied to the gate driver 11 by the display control circuit4 via the terminals 113 to 115. When a reset signal (CLR) is supplied,the netA, netB and gate line 13G transition to L (low) level.

From time tO to tl of FIG. 9, an L level clock signal (CKA) is suppliedto the terminals 116 and 117, and an H level clock signal (CKB) issupplied to the terminals 118 and 119. Thus, the TFT-G turns on and theTFT-H turns off such that the netB is charged to H level. Further, theTFT-C and TFT-D turn on and the TFT-F turns off such that the netA ischarged to L level, i.e. the level of the power supply voltage (VSS),and the L-level potential is output at the terminal 120.

Next, at time t1, the clock signal (CKA) goes to H level and the clocksignal (CKB) goes to L level, turning off the TFT-G and turning on theTFT-H such that the netB is charged to L level. Then, the TFT-C and theTFT-D turn off, which maintains the potential of the netA at L level,and the L level potential is output at the terminal 120.

At time t2, the clock signal (CKA) goes to L level and the clock signal(CKB) goes to H level, and a set signal (S) is supplied to the terminals111 and 112 via the gate line 13G: GL(n−1). This turns on the TFT-B andcharges the netA to H level. Further, the TFT-J turns on, the TFT-Gturns on and the TFT-H turns off such that the netB is maintained at Llevel. The TFT-C and the TFT-F turn off such that the potential of thenetA does not decrease, i.e. is maintained. Meanwhile, since the TFT-Dis on, the L-level potential is output at the terminal 120.

At time t3, the clock signal (CKA) goes to H level and the clock signal(CKB) goes to L level, turning on the TFT-F and turning off the TFT-D.Since the capacitor Cbst is provided between the netA and terminal 120,the netA is charged to a potential higher than the H level of the clocksignal (CKA) as the potential of the terminal 116 of the TFT-Fincreases. Meanwhile, the TFT-G and the TFT-J are off and the TFT-H ison such that the potential of the netB is maintained at L level. Sincethe TFT-C is off, the potential of the netA does not decrease, and theH-level potential (i.e. selection voltage) of the clock signal (CKA) isoutput at the terminal 120. Thus, the gate line 13G: GL(n) connectedwith the terminal 120 is charged to H level, and is in the selectedstate.

At time t4, the clock signal (CKA) goes to L level and the clock signal(CKB) goes to H level, turning on the TFT-G and turning off the TFT-Hsuch that the netB is charged to H level. Thus, the TFT-C turns on andthe netA is charged to L level. Meanwhile, the TFT-D is on and the TFT-Fis off such that the L-level potential (i.e. non-selection voltage) isoutput at the terminal 120, and the gate line 13G: GL(n) is charged to Llevel.

Thus, as a set signal (S) is provided to a gate line 13G from theterminal 120 of the gate driver 11, this gate line 13 enters theselected state. The liquid crystal display device 1 uses a plurality ofgate drivers 11 connected with the gate lines 13G to sequentially scanthe gate lines 13G and uses the source driver 3 to supply data signalsto the source lines 15S to display an image on the display panel 2.

In the above first embodiment, a plurality of gate drivers 11 areprovided for each gate line 13G within the display region. Each gateline 13G is sequentially driven by a scan signal provided by the gatedrivers 11 connected with this gate line 13G. This reduces dullness of ascan signal in a gate line compared with conventional implementationswhere a gate driver is provided outside the display region and a scansignal is input at one end of each gate line, thereby driving the gatelines at high speed. Also, since a plurality of gate drivers 11 areconnected with one gate line 13G, even when the gate line 13G is brokenat one position, a scan signal is supplied from other portions,maintaining appropriate image display.

Further, in the above first embodiment, control signals such as clocksignals and power supply voltage signals supplied to the gate drivers 11provided in the display region are input through the portions of thepicture frame region that are provided along the side of the displaypanel 2 where the source driver 3 is provided, as shown in FIGS. 1 and3, for example. Thus, the picture frame width of the portions of theperipheral region along the other sides, where the source driver 3 isnot present, may be reduced.

Further, in the above first embodiment, a shield layer 16 is providedbetween the switching elements and lines of the gate drivers 11 providedin the display region and the pixel electrodes 17, thereby preventinginterference between the gate drivers 11 and pixel electrodes 17 suchthat an image can be displayed appropriately.

Further, in the above first embodiment, a line 15L2 is provided in apixel region in which a capacitor Cbst constituting a part of a gatedriver 11 is provided to extend from the contact CH2 to the vicinity ofthe contact CH1 such that the aperture ratio of this pixel region isequal to that of other pixel regions, as shown in FIGS. 5B and 8E. Thisresults in a generally uniform aperture ratio among the pixel regions,reducing color irregularity or the like.

Second Embodiment

The above first embodiment describes an implementation where all theelements constituting each gate driver 11 are provided inside thedisplay region. The present embodiment describes an implementation wheresome of the elements constituting each gate driver 11 are providedinside the display region. FIG. 10A is a schematic diagram showing aportion of each gate driver 11 provided inside the display region andthe other portions of the gate drivers 11 provided outside the displayregion. As shown in FIG. 10A, in the present embodiment, in the displayregion 20A of the active-matrix substrate 20a are provided, in additionto the gate lines 13G and source lines 15S, TFTs-F and capacitors Cbst,lines 15L1 for supplying the TFTs-F with clock signals (CKA, CKB), andlines 13N connecting the TFTs-F and capacitors Cbst with the netA.

The portions of the gate drivers 11 except the TFTs-F and capacitorsCbst are provided in the external region 2A (i.e. outside the displayregion) of the display region 20A of the active-matrix substrate 20 a,on one end of each gate line 13G. These portions of the gate drivers 11are electrically connected with the TFTs-F and capacitors Cbst via lines13N.

How the TFTs-F and capacitors Cbst provided in the display region 20 aare connected will be described below. FIG. 10B is an enlarged plan viewof pixel regions in which the TFT-F and the capacitor Cbst of a gatedriver 11 for driving the lines GL(n−1) and GL(n) are provided. As shownin FIG. 10B, lines 13N are provided that are substantially parallel tothe gate lines 13G in the pixel regions P11 to P13 and P21 to P23, eachconnecting to the netA of a gate driver 11 provided outside the displayregion.

As is the case in the first embodiment, a capacitor Cbst and a line 15L2are provided in the pixel regions P11 and P21, and the electrode 15 c ofthe capacitor Cbst is connected with the line 13N via the contact CH2.Further, a line 15L1 to which a clock signal (CKA) is supplied isprovided in the pixel regions P12 and P22. A line 15L1 to which a clocksignal (CKB) is supplied is provided in the pixel regions P13 and P23.As is the case in the first embodiment, the gate line 13G is connectedwith the drain terminal via the contact CH5.

In the above second embodiment, the TFTs-F and capacitors Cbst areprovided in the display region 20A; alternatively, for example, TFTs-Dmay be provided in the display region 20A. A TFT-F has the function ofswitching the driving of a gate line 13G between on and off, while aTFT-D has the function of maintaining the driving of a gate line 13G atthe off state in response to a supplied clock signal. These TFTs, whichhave a larger output than other TFTs, may be provided in the displayregion 20A to disperse heat emitted by the TFTs, thereby increasing themargin against a malfunction.

Third Embodiment

The present embodiment describes a liquid crystal display deviceincluding a display panel 2 according to the first embodiment containedin a lens-integrated housing. FIG. 11 is a schematic cross-sectionalview of the liquid crystal display device according to the presentembodiment. As shown in FIG. 11, the liquid crystal display device 1Aincludes a lens-integrated housing 60 (i.e. an example of a housing), adisplay panel 2 and a backlight 70.

The lens-integrated housing 60 includes a housing body 60A (i.e. anexample of a second cover portion) and a cover 60B (i.e. an example of afirst cover portion). The housing body 60A includes a housing side 61and a housing bottom 62. The housing side 61 is translucent and isprovided on the side 2 s of the display panel 2, which is parallel tothe Y axis of the display panel 2 shown in FIG. 2, so as to cover theside 2 s. The housing bottom 62 is provided below the backlight 70 so asto cover the bottom of the backlight 70.

The cover 60B includes a lens 63 and a flat plate 64. The lens 63 has aviewer's side (in the Z-direction) that is curved in shape. The lens 63is located to overlie a region that includes the picture frame region10F, display region 10D and panel-housing region 60G of the displaypanel 2. The display region 10D is the portions of the lens 63 that aredefined between the inner edge 63 b of the display region 10A and theinner edge 10Fb of the picture frame region 10F. The panel-housingregion 60G is defined between the side 2 s of the display panel 2 andthe side 60 s of the housing side 61. The outer edge 63 a of the lens 63is connected with the housing side 61 at the upper edge of its side 61s. The flat plate 64 is translucent and is located to overlie thedisplay region 10B. The light-emitting surface of the flat plate 64 isconstructed so as to be substantially parallel to the display surface 2p of the display panel 2.

As discussed in connection with the first embodiment, the display panel2 has gate drivers 11 located in the display region 10A. As shown inFIGS. 2 and 3, control signals such as clock signals are suppliedthrough the portions of the picture frame region through which controlsignals and power supply voltage signals are supplied, i.e. the portionsof the picture frame region that are provided along one side parallel tothe X axis. Thus, in the display panel 2, the width of the portions ofthe picture frame that are provided along another side parallel to the Xaxis and the two sides parallel to the Y axis may be reduced. In thepresent embodiment, the display panel 2 is contained in thelens-integrated housing 60 such that the portions of the picture frameregion 10F that are provided along the two sides parallel to the Y axisoverlie the lens 63. As shown in FIG. 12, a light beam (indicated by abroken line) emitted from the display surface 2 p of the display panel 2is refracted by the curved surface of the lens 63 and advancesstraightforward in a direction perpendicular to the display surface 2 p(i.e. positive Y-direction). As a result, an image from the displayregion 10A is displayed on the viewer's side, and the picture frameregion 10F is less visible.

Thus, a display panel 2 with two opposite sides that have narrowerpicture frame portions may be employed to reduce the size of the lens 63compared with conventional implementations, thereby reducing the weightof the lens-integrated housing 60 and reducing manufacturing costs. Thatis, in a conventional display panel 2 with gate drivers 11 providedoutside the display region 10A, the terminals and other components forsupplying data signals and scan signals are located in the picture frameportions along two adjacent sides. In a conventional display panel,these picture frame region portions overlie the lens 63. As the width ofthe picture frame region 1OF increases, the thickness of the lens 63increases. Thus, if a conventional display panel is employed, a lens 63with a larger size must be used than in the display panel 2 of thepresent embodiment, making it difficult to reduce the weight of thelens-integrated housing 60 or reduce manufacturing costs.

Fourth Embodiment

Starting from the above first embodiment, the display region may bedivided into sub-regions arranged in the direction in which the gatelines 13G are arranged and data may be written for each sub-region. FIG.13 is a schematic diagram of an active-matrix substrate 120 a accordingto the present embodiment without the source lines 15S and terminals 12s. In FIG. 13, the components that are the same as the correspondingones of the above first embodiment are labeled with the same referencenumerals. The differences from the first embodiment will be describedbelow.

The display region 20A of FIG. 13 includes three separate sub-regionsS1, S2 and S3 arranged in the direction in which the gate lines 13G arearranged, i.e. in the Y-direction. In this implementation, the gatelines 13G in the sub-region S3 are driven by the gate driver groups11_S31 and 11_S32. Each gate driver 11 in the gate driver groups 11_S31and 11_S32 is provided between two gate lines 13G in the sub-region S3,and no gate driver 11 is provided in the portions of the columns havingthe gate driver groups 11_S31 and 11_S32 that belong to the othersub-regions (S1 and S2). Each gate driver 11 is connected with aterminal 12 g via a line 15L1 and, in response to control signalssupplied via the terminal 12 g (clock signals, for example), drives thecorresponding one of the gate lines 13G.

The gate lines 13G in the sub-region S2 are driven by the gate drivergroups 11_S21 and 11_S22. Further, the gate lines 13G in the sub-regionS1 are driven by the gate driver groups 11_S11 and 11_S12. Each gatedriver 11 of these gate driver groups is located between two gate lines13G in the sub-region (S2 or S1) in which it is located. No gate driver11 is provided in the portions of the columns having these gate drivergroups that belong to the other sub-regions.

FIG. 13 shows an implementation where two gate drivers 11 drive one gateline 13G; alternatively, only one gate driver 11 may drive a gate line13G, or three or more gate drivers may drive a gate line.

How data from the source driver 4 is written into the display region 20Aof the implementation of FIG. 13 will be described. Signals of data tobe displayed in the sub-regions S1, S2 and S3 are provided from thesource driver 4 to the source lines 15S (not shown) in the displayregion 20A on a frame basis. Start pulse signals are supplied from thedisplay control circuit 4 to the gate driver groups so as to startdriving the gate lines 13G in the sub-regions at a time point at whichthe data signals are written into the sub-regions S1, S2 and S3.

As shown in FIG. 14, in each frame, the data signals for all thesub-regions are output. Beginning at time t1 at which the start pulsesignals are supplied, the gate driver groups 11_S11 and 11_S12sequentially drive the gate lines 13G in the sub-region S1. Thus, datasignals are written into the sub-region S1 at the time point at whichthe gate lines 13G in the sub-region S1 are driven.

At time t2 at which set signals are provided by the gate driver groups11_S11 and 11_S12 to the gate lines 13G of the sub-region S2, startpulse signals are supplied to the gate driver groups 11_S21 and 11_S22.After the start pulse signals are supplied, the gate driver groups11_S21 and 11_S22 sequentially drive the gate lines 13G of thesub-region S2. Thus, data signals are written into the sub-region S2 atthe time point at which the gate lines 13G in the sub-region S2 aredriven.

At time t3 at which set signals are provided by the gate driver groups11_S21 and 11_S22 to the gate lines 13G of the sub-region S3, startpulse signals are supplied to the gate driver groups 11_S31 and 11_S32.After the start pulse signals are supplied, the gate driver groups11_S31 and 11_S32 sequentially drive the gate lines 13G of thesub-region S3. Thus, data signals are written into the sub-region S3 atthe time point at which the gate lines 13G in the sub-region S3 aredriven.

Thus, when data is written to the entire display region 20A, datasignals for all the sub-regions are supplied to the source lines 15S(not shown), and start pulse signals are supplied such that, in the timeperiod during which data for each sub-region is written, the gate lines13G in this sub-region start to be driven. Thus, data is sequentiallywritten in the order of the sub-regions S1, S2 and S3.

How data signals are written at different frequencies for differentsub-regions will be described below. For example, if data signals arewritten to the sub-regions S1 and S3 at a frequency of 60 Hz and datasignals are written to the sub-region S2 at a frequency of 1 Hz, for thefirst frame, data signals are written to the sub-regions as shown inFIG. 15 by sequentially driving the gate lines 13G in the order of thesub-regions S1 to S3, as described above.

For the second to sixtieth frames, in the time period during which datais written for the sub-regions S1 and S3 (i.e. the selection periods forthe gate lines 13 of the sub-regions S1 and S3), data signals for imagesto be displayed in the sub-regions S1 and S3 are provided from thesource driver 4 to the source lines 15S (not shown). Further, in theperiod during which data is written for the sub-region S2, data signalswith the smallest amplitude is provided by the source driver 4. Datasignals with the smallest amplitude may be, for example, data signalsindicating black if the active-matrix substrate 120 a is in normallyblack display mode. In the period during which data is written to thesub-region S2 (i.e. the selection period for the gate lines 13 of thesub-region S2), the display control circuit 4 does not supply controlsignals (such as clock signals) and does not drive the gate drivergroups 11_S21 and 11_S22.

Thus, as shown in FIG. 16, in the period during which data is writtenfor the sub-region S1 (t1 to t2), the gate lines 13G of the sub-regionS1 are sequentially driven such that data is written to the sub-regionS1. Then, in the period during which data is written to the sub-regionS2 (t2 to t3), the gate lines 13G of the sub-region S2 are not drivenand data signals indicating black are output such that no data iswritten to the sub-region S2. After the period during which data iswritten for the sub-region S2, the gate lines 13G of the sub-region S3are sequentially driven and data is written to the sub-region S3. Thus,as the gate lines 13G of the sub-region S2 are only driven for the firstframe, data is written to the sub-region S2 at 1 Hz and data is writtento the other sub-regions S1 and S3 at 60 Hz.

The present embodiment describes an implementation where data is writtento the sub-regions at 60 Hz and 1 Hz; alternatively, data may be writtento the sub-regions at frequencies of 10 Hz and 0.1 Hz, for example. Thepresent embodiment only requires that data be written to the sub-regionsat at least two different frequencies. Providing a sub-region to whichdata is written at a lower frequency than to other sub-regions reducespower consumption.

Fifth Embodiment

Starting from the above first embodiment, the gate lines 13G may bedriven on a single-row basis or a multiple-row basis depending on theimage to be displayed. The following describes such an arrangement.

To improve the quality of moving images displayed, data may be writtenat a frequency of 120 Hz or 240 Hz. The higher the frequency, the morequickly the liquid crystal layer must be charged, and, to address this,a plurality of gate lines may be driven simultaneously. In such a case,for example, the gate lines in the N+1th and Nth rows are drivensimultaneously such that data signals written to the pixels of the Nthrow are also written to the pixels of the N+1th row. In the case ofmoving images, the pixels of the same column in the Nth and N+1th rowsreceive data signals indicating substantially the same color, and, assuch, a pixel having a data signal that is intended for a pixel in anadjacent row rarely poses a problem when displaying an image. On theother hand, in the case of a still image or video with sharp contours,writing to a pixel a data signal intended for a pixel in an adjacent rowmay cause a problem: for example, an image may be blurred. In thepresent embodiment, the gate lines 13G are driven on a single-row basiswhen an image such as a still image is to be displayed, and the gatelines 13G are driven on a multiple-row basis when moving images are tobe displayed.

FIG. 17 is a schematic view of an active-matrix substrate according tothe present embodiment. In FIG. 17, for convenience, the source lines15S and terminals 12 s are not shown and the gate drivers 11 and lines15L1 are simplified. Further, in the present implementation, forconvenience, gate lines 13G: GL(1) to GL(7) are provided on theactive-matrix substrate 220 a.

A gate driver group 11_a and gate driver group 11_b are provided on theactive-matrix substrate 220 a. Each of the gate driver group 11_a andgate driver group 11_b includes a plurality of gate drivers 11 eachconnected with one of the gate lines 13G: GL(1) to GL(7). The gatedriver group 11_a includes gate drivers 11(a 1) to (a7). The gate drivergroup 11_b includes gate drivers 11(b 1) to (b7). For example, the gateline 13G: GL(1) is driven by the gate drivers 11(a 1) and 11(b 1). Thegate line 13G: GL(2) is driven by the gate drivers 11(a 2) and 11(b 2).Similarly, each of the gate lines 13G: GL(3) to GL(7) is driven by twogate drivers 11, belonging to the gate driver groups 11_a and 11_b,connected with the corresponding gate line 13G.

When an image such as a still image is to be displayed, as is the casein the first embodiment, the gate driver 11 of the gate driver group11_a and the gate driver 11 of the gate driver group 11_b for each gateline 13G are synchronized to drive this gate line 13G.

When moving images are to be displayed, start pulse signals are suppliedto the gate driver group 11_a and the gate driver group 11_b atdifferent time points. FIG. 18 illustrates the timing for supplyingstart pulse signals to the gate driver groups 11_a and 11_b from thedisplay control circuit 4. In the example of FIG. 18, a start pulsesignal Sa is supplied to the gate driver group 11_a, and then a startpulse signal Sb is supplied to the gate driver group 11_b. That is, astart pulse signal for the gate driver group 11_b is supplied at a timepoint at which the driving time for the gate line 13G of the first row(GL(1)) by the gate driver 11 of the gate driver group 11_a ends.

FIG. 19 illustrates the timing in which the gate lines 13G: GL(1) toGL(7) are driven when start pulse signals are supplied to the gatedriver groups 11_a and 11_b. Each of the gate lines 13G: GL(1) to GL(7)is driven by the corresponding gate driver 11 of the gate driver group11_a and then is driven by the corresponding gate driver 11 of the gatedriver group 11_b. Thus, as illustrated in FIG. 19, each gate line 13Gis driven twice successively. Then, at the time point at which the gateline 13G of the Nth row is driven by the gate driver group 11_b, thegate line 13G of the N+1th row is driven by the gate driver group 11_asuch that the gate lines 13G of the Nth and N+1th rows are drivensimultaneously.

The source driver 3 provides data signals for the pixels of each row tothe source lines 15S (not shown) at a time point at which the gate line13G of this row is driven for the second time, i.e. the correspondinggate driver 11 of the gate driver group 11_b drives this gate line 13G.

FIG. 20 is an enlarged schematic diagram of an area containing thepixels 17_1, 17_2 and 17_3 formed by the gate lines 13G: GL(1) to GL(3),respectively, and the source line 15S_x of the Xth column, shown in FIG.17. From the pixel 17_1 of the row GL(1) onward, a data signal for thepixel is provided to the source line 15S_x at a time point at which thegate line 13G of the associated row is driven for the second time.

As shown in FIG. 21, the data D1 for the pixel 17_1 is written to thepixel 17_1 of the row GL(1) at a time point at which the gate line 13G:GL(1) is driven for the second time. Then, the data D1 for the pixel17_1 of the preceding row is written to the pixel 17_2 of the row GL(2)at the first driving time point, and the data D2 for the pixel 17_2 iswritten thereto at the second driving time point. The data D2 for thepixel 17_2 of the preceding row is written to the pixel 17_3 of the rowGL(3) at the first driving time point, and the data D3 for the pixel17_3 is written thereto at the second driving time point. Similarly, thedata Dn−1 for the pixel of the preceding row is written to the pixel17_7 (not shown) of the row GL(7) at the first driving time point, andthe data Dn for the pixel 17_n is written thereto at the second drivingtime point. Thus, for the pixel of a given row, the data that issupposed to be written to that pixel is written thereto at the timepoint at which the gate line 13G of this row is driven for the lasttime.

The present embodiment shows an implementation where one gate line 13Gis driven by two gate drivers 11 at different time points to drive twogate lines 13G simultaneously; alternatively, three or more gate drivers11 may drive one gate line 13G. The present embodiment only requiresthat one gate line 13G is driven by at least the number of gate drivers11 that is equal to the number of gate lines 13G that are drivensimultaneously. That is, if N gate lines 13G (N>2) are to be drivensimultaneously, N different data signal voltages are applied to onepixel. Of course, in such a case, for a given pixel, a data signal thatis supposed to be written to this pixel is supplied as the final writtensignal for this pixel.

Sixth Embodiment

In the above first embodiment, the line 15L1 formed by the source linelayer 15 is provided on top of the gate line layer 13, with the gateinsulating film 21 being present in between, and the gate lines 13Gcross the lines 15L1, with the gate insulating film 21 being present inbetween (see FIG. 7C). The parasitic capacitance at the intersection ofa line of the gate line layer 13 and a line of the source line layer 15is relatively large, potentially causing a disturbance, delay or thelike in clock signals or the like supplied by a line 15L1. The presentembodiment describes an implementation where the line 15L1 is formedsuch that the gate line 13G does not cross the line 15L1, with the gateinsulating film 21 being present in between.

FIG. 22 is a schematic plan view of the pixel region 203R in which aswitching element (TFT-F) constituting a part of the gate driver 11described above is provided. In FIG. 22, the line 15L1 formed by thesource line layer 15 and the drain electrode 15 d of the TFT-F areconnected with a connection line 17C via a contact CH6 that crosses thegate line 13G. The connection line 17C is provided in the same layer asthe pixel electrode 17.

FIG. 23 is a schematic cross-sectional view of the contact CH6 of FIG.22 taken along line V-V. As shown in FIG. 23, on top of the gate line13G are provided a gate insulating film 21 and a protection film 22. Theline 15L1, formed by the source line layer 15, is provided on top of theprotection film 22 so as to be broken into separate portions above thegate line 13G, with the gate insulating film 21 being present inbetween. On top of the line 15L1 is provided a protection film 23 madeof an insulating film and having a larger thickness than the gateinsulating film 21. On top of the protection film 23 is provided ashield layer 16 made of a transparent conductive film, and, on top ofthe shield layer 16 is provided an interlayer insulating film 24.Contact holes H31 and H32 are provided near the opposite ends of theseparated line 15L1 portions to extend through the protection film 23,shield layer 16 and interlayer insulating film 24. A connection line 17Cmade of ITO, similar to the pixel electrode 17, is provided on thecontact holes H31 and H32, and the separate portions of the line 15L1are connected with the connection line 17C at the contact holes H31 andH32.

Thus, the separate portions of the line 15L1 above the gate line 13G areconnected via the connection line 17C, thereby allowing control signalssuch as clock signals from the terminals 12G to be supplied to the gatedrivers 11. Further, the line 15L1 is not present at the location whereit would otherwise cross the gate line 13G, with the gate insulatingfilm 21 being present in between, reducing the signal disturbance ordelay caused by the electric capacitance of the gate line 13G.

Seventh Embodiment

The present embodiment describes an implementation where a portion ofthe gate line 13G near the intersection of itself and the source line15S is smaller than the maximum width of the gate line 13G such that thegate line 13G can be easily broken.

FIG. 24A is an enlarged schematic view of an area containing theintersection of a gate line 13G and a source line 15S. As shown in FIG.24A, an image display TFT (TFT-PIX) is connected with the gate line 13Gand source line 15S, and a pixel electrode 17 is connected with theTFT-PIX. The gate line 13G is constructed such that each of a portionnear the intersection of the gate line and source line 15S that isadjacent its connection with the gate terminal of the TFT-PIX, (xR), anda portion near the intersection of the gate line and source line 15Sthat is not adjacent its connection with the TFT-PIX, (xL), has aportion with a width h that is smaller than the maximum width H of thegate line 13G. Each of the portions of the gate line 13G that have thewidth h are narrower and therefore can be easily broken than otherportions of the line. In the present embodiment, the maximum width H ofthe gate line 13G may be about 10 μm, for example, and the width h maybe about 5 μm, for example.

As is the case in the first embodiment, a plurality of gate drivers 11are provided, each corresponding to one of the gate lines 13G. Thus,when there is a short circuit at the intersection of a gate line 13G andsource line 15S and between two adjacent gate drivers 11 (not shown)provided for the same row, the gate line 13G may be broken at theportions of the gate line 13G that have the width h to cut off theportion of the gate line 13G where there is a short circuit. Even whenthe gate line 13G is broken, that one of the gate line 13G portionsseparated at the source line 15S to which the TFT-PIX is connected(hereinafter referred to as TFT-PIX connection portion) is driven by agate driver 11 (not shown) that is located on the TFT-PIX connectionportion. That one of the gate line 13G portions separated at the sourceline 15S to which the TFT-PIX is not connected (hereinafter referred toas TFT-PIX non-connection portion) is driven by a gate driver 11 (notshown) that is located on the TFT-PIX non-connection portion. That is,even when the gate line 13G is broken, the TFTs-PIX connected with thebroken gate line 13G can function such that supplying data signals tothe source lines 15S causes the pixel at the broken location to displayan image.

The gate line 13G of FIG. 24A is an implementation where a portionthereof near the intersection thereof and the source line 15S has asmaller width than the maximum width of the gate line 13G;alternatively, the gate line may be constructed as shown in FIGS. 24Band 24C, for example. Each of FIGS. 24B and 24C is an enlarged schematicview of a portion of a gate line 13G near the intersection thereof and asource line 15S.

As shown in FIG. 24B, each of the portions of the gate line 13G near theintersection (xR, xL) has a portion branched into two gate linesub-portions 13G_a and 13G_b. In the implementation of FIG. 24C, thegate line 13G is branched into two gate line sub-portions 13G_c and13G_d at the portions near the intersection (xR, xL), and each of thegate line sub-portions 13G_c and 13G_d is continuous at the intersectionportion (xc). Each of the gate line sub-portions 13G_a and 13G_b andgate line sub-portions 13G_c and 13G_d has a width h that is smallerthan the maximum width H.

If a gate line 13G has a portion with a small width has in FIG. 24A, theresistance is larger in such a portion, potentially causing a signaldelay. In the implementations of FIGS. 24B and 24C, each of the gateline sub-portions (13G_a, 13G_b, 13G_c and 13G_d) has a width h that issubstantially equal to that of FIG. 24A; however, in the implementationsof FIGS. 24B and 24C, portions of a small width h are provided inparallel, reducing the resistance compared with the implementation ofFIG. 24A. The sum of the widths h may be equal to or larger than thewidth H. That is, the gate line may be constructed such that h×2≧H if itis branched into two. Thus, the resistance of the entire portion with abranch is equal to or smaller than the resistance of the other portions(without a branch).

Eighth Embodiment

In the above first embodiment, luminance unevenness or the like may beproduced by the difference between the aperture ratio of a pixel regionwith an element that constitutes a part of a gate driver 11 (hereinafterreferred to as gate driver region) and that of a pixel region without anelement constituting a part of a gate driver 11 (hereinafter referred toas no-gate driver region). In view of this, in the present embodiment, ano-gate driver region is constructed so as to reduce the differencebetween the aperture ratio of the gate driver regions and that of theno-gate driver regions.

FIG. 25A is a schematic plan view of a no-gate driver region accordingto the present embodiment. In FIG. 25A, the components that are the sameas the corresponding ones of the first embodiment are labeled with thesame reference numerals as in the first embodiment. As shown in FIGS. 8Ato 8D for the above first embodiment, in a gate driver region, a line15L1 formed by the source line layer 15 is provided to be generallyparallel to the source lines 15S. In view of this, in a no-gate driverregion, a dummy line 15L4 (i.e. adjustment line) formed by the sourceline layer 15 is provided to be generally parallel to the source lines15S, as shown in FIG. 25A. The dummy line 15L4 has a length and widththat are substantially equal to those of the line 15L1. Although theregion where light is blocked by the black matrix is not indicated inFIG. 25A, the area in which the gate line 13G, dummy line 15L4 andsource line 15S are provided is shielded by the black matrix, as is thecase in FIG. 6 of the above first embodiment such that the apertureratio is substantially equal to that of the gate driver region. Thisconstruction reduces the difference between the aperture ratio of theno-gate driver regions and that of the gate driver regions, reducingluminance unevenness or the like.

Further, as shown in FIGS. 8A, 8D and 8E for the above first embodiment,in a gate driver region, a line 13N formed by the gate line layer 13 isprovided to be generally parallel to the gate line 13G. In view of this,as shown in FIG. 25A, in a no-gate driver region, a dummy line 13N′(i.e. adjustment line) formed by the gate line layer 13 is provided tobe generally parallel to the gate line 13G. In this implementation, thedummy lines 13N′ and 15L4 are connected via the contact CH2. If anauxiliary capacitance is to be provided in a pixel, the dummy line 13N′may be used as an auxiliary capacitance line and the dummy line 15L4 maybe used as a line for supplying a voltage signal to the auxiliarycapacitance line. Alternatively, the dummy line 13N′ may be used as acommon electrode line and the dummy line 15L4 may be used as a line forsupplying a voltage signal to the common electrode line. Providing adummy line 13N′ reduces the difference between the parasitic capacitancebetween the source line layer 15 and gate line layer 13 in the no-gatedriver regions and that for the gate driver regions, reducing displayunevenness. FIG. 25A shows an implementation where the dummy lines 13N′and 15L4 are connected with each other within the pixel; alternatively,if voltage signals for the common electrode and auxiliary capacitanceare supplied to these dummy lines separately, these dummy lines do notneed be connected with each other within the pixel.

Example Application of Eighth Embodiment

In the above eighth embodiment, a parasitic capacitance is producedbetween the source line 15S and the dummy line 15L4 provided in theno-gate driver region. As discussed above, a constant voltage signal issupplied to the dummy line 15L4 for controlling the potential of thecommon electrode and auxiliary capacitance. On the other hand, in thegate driver region, a parasitic capacitance is produced between thesource line 15S and a node in the gate driver 11 such as the netA ornetB formed by the gate line layer 13. During the period where the TFT-Cof the gate driver 11 is on, the netA or netB is fixed to the powersupply voltage VSS; during the period where the TFT-C is off, it is in afloating state.

The no-gate driver region has a parasitic capacitance between the sourceline 15S and the dummy line 15L4 with a fixed, generally constantpotential, and the gate driver region has a parasitic capacitancebetween the source line 15S and a node that may be in a floating state;as such, there is a difference between the capacitance of the sourceline 15S in the no-gate driver regions and that for the gate driverregions. As a result, there is a difference between the charging rate ofthe source line 15S encountered when data is written to a gate driverregion and that for a no-gate driver region, causing luminanceunevenness among the gate driver regions and no-gate driver regions.Particularly, luminance unevenness can be easily perceived when ahalf-tone image is displayed. In view of this, when data for a half-toneimage is to be written to a gate driver region, this image data may beadjusted. A specific arrangement for this will be described below.

FIG. 25B is a schematic view of an arrangement of the liquid crystaldisplay device 1 according to the present example application. As shownin FIG. 25B, in addition to the components of the first embodiment, animage adjustment circuit 6 is provided. The image adjustment circuit 6is electrically connected with the display control circuit 4, sourcedriver 3 and power supply 5. The image adjustment circuit 6 supplies thesource drive 3 with a data signal with a voltage in the level equal tothe voltage of a data signal to be written to a no-gate driver regionplus a predetermined amount.

FIG. 25C shows drive waveforms for a pixel encountered when anunadjusted data signal and a data signal adjusted by the imageadjustment circuit 6 are supplied to the source line 15S of the no-gatedriver region. As shown in FIG. 25C(a), if an unadjusted data signal D1is supplied to the source line 15S at time t1, at which the gate line13G of the no-gate driver region is driven, the potential of the sourceline 15S of the gate driver region fluctuates as indicated by the waveP1. The potential of the source line 15S of the no-gate driver regionfluctuates as indicated by the wave P2. That is, the potential of thepixel of the no-gate driver region is smaller than the potential of thepixel of the gate driver region, causing luminance unevenness among theno-gate driver regions and gate driver regions.

To address this, the image adjustment circuit 6 supplies the pixel of ano-gate driver region with a data signal D2 (indicated by a broken line)with a voltage in the level equal to the voltage of the data signal D1plus a predetermined amount. Referring to (b) of FIG. 25C, when a datasignal D2 is supplied to the pixel of the no-gate driver region, thepotential of the source line 15S of the no-gate driver region isgenerally equal to the potential of the source line 15S of the gatedriver region. This reduces luminance unevenness among the gate driverregions and no-gate driver regions. The above example applicationdescribes an implementation where the voltage of the data signal writtento a no-gate driver region is increased; alternatively, the potential ofthe data signal written to a gate driver region may be reduced by apredetermined amount.

Ninth Embodiment

The present embodiment describes an implementation where each pixel iscomposed of two sub-pixels with different luminance levels to improveviewing angle characteristics when the display mode of the liquidcrystal display device 1 is the vertical alignment (VA) mode.

FIG. 26 shows an equivalent circuit of a pixel according to the presentembodiment. As shown in FIG. 26, the pixel PIX is composed of asub-pixel PIX1 and a sub-pixel PIX2. Further, auxiliary capacitancelines CS1 and CS2 extending generally parallel to the gate line 13G areprovided to sandwich the gate line 13G: GL(n). Two switching elements T1and T2, each composed of a thin-film transistor, are connected to thegate line 13G: GL(n) and the source line 15S.

The pixel electrode 17a and one of the electrodes of a capacitor (i.e.auxiliary capacitance electrode) Ccsl are connected with the drainterminal of the switching element T1, while the other electrode of thecapacitor Ccs1 is connected with the auxiliary capacitance line CS1(n).The sub-pixel PIX1 includes a liquid crystal capacitance LC1 formed bythe pixel electrode 17 a (i.e. first pixel electrode), liquid crystallayer and common electrode (not shown), and an auxiliary capacitance C1of the capacitor Ccs1.

The pixel electrode 17 b (i.e. second pixel electrode) and one of theelectrodes of a capacitor (i.e. auxiliary capacitance electrode) Ccs2are connected with the drain terminal of the switching element T2, whilethe other electrode of the capacitor Ccs2 is connected with theauxiliary capacitance line CS2(n). Thus, the sub-pixel PIX2 includes aliquid crystal capacitance LC2 formed by the pixel electrode 17 b,liquid crystal layer and common electrode (not shown), and an auxiliarycapacitance C2 of the capacitor Ccs2.

The auxiliary capacitance lines CS1(n) and CS2(n) are connected withauxiliary capacitance signal lines CSL1 and CSL2, respectively, providedin the display region. The auxiliary capacitance signal lines CSL1 andCSL2 supply the auxiliary capacitance lines CS1(n) and CS2(n),respectively, with voltage signals VCS1 and VCS2, respectively, from acontrol circuit (not shown) in the source driver 3 (not shown). Thevoltage signals VCS1 and VSC2 are supplied to the auxiliary capacitancelines CS1(n) and CS2(n), respectively, such that the phase of thepotential of the auxiliary capacitance line CS1(n) is opposite the phaseof the potential of the auxiliary capacitance line CS2(n). The voltagesignals VCS1 and VCS2 are positive and negative voltage signals,respectively, each with an increase or decrease in amplitude withrespect to the potential of the common electrode (not shown), and thepolarity is reversed by the control circuit (not shown) on aframe-to-frame basis.

As is the case in the first embodiment, the gate line 13G: GL(n) isdriven by a gate driver 11 provided in the display region. A positive ornegative data signal with respect to the potential of the commonelectrode (not shown) is supplied to the source line 15S. The datasignal is supplied to the source line 15S while its polarity is reversedon a frame-to-frame basis.

FIGS. 27A and 27B schematically show pixel regions where gate drivers 11and auxiliary capacitance signal lines CSL1 and CSL2 are provided. Thepixel region is continuous where the row 200 x connects therepresentations of FIGS. 27A and 27B.

As shown in FIGS. 27A and 27B, pairs of auxiliary capacitance lines CS1and CS2 are provided, where the lines of each pair sandwich a gate line13G: GL(n−2) to GL(n+1). In this implementation, the auxiliarycapacitance lines CS1 and CS2 are arranged such that, for each gate line13G, the auxiliary capacitance lines CS1 and CS2 are switched inposition. Further, although FIGS. 27A and 27B do not have the character“TFT-”, “A” to “J” in FIGS. 27A and 27B indicate TFT-A to TFT-Jconstituting parts of gate drivers 11. As is the case in the firstembodiment, the elements constituting a gate driver (TFT-A to J andCbst) are dispersed in pixel regions. Further, lines 13N connectingelements and lines 15L1 for supplying control signals to elements areprovided in pixel regions.

No element constituting a part of the gate driver 11 is provided in thepixel regions of the columns 211 x to 214 x in FIG. 27B. In thisimplementation, auxiliary capacitance signal lines CSL1 and CSL2 forsupplying voltage signals VCS1 and VCS2 to auxiliary capacitance linesCS1 and CS2 are provided in the pixel regions of the columns 211 x to214 x. Auxiliary capacitance signal lines CSL1 are provided in thecolumns 211 x and 212 x. In the columns 211 x, an auxiliary capacitancesignal line CSL1 is not connected with an auxiliary capacitance line CS1and is connected with an auxiliary capacitance line CS1 in the column212 x via an auxiliary capacitance signal line CSL1′, which is anextension of a branched auxiliary capacitance signal line CSL1 in thecolumn 212 x. Further, auxiliary capacitance lines CSL2 are provided inthe columns 213 x and 214 x. In the column 213 x, an auxiliary columnsignal line CSL2 is not connected with an auxiliary capacitance line CS2and is connected with an auxiliary capacitance line CS2 via an auxiliarycapacitance signal line CSL2′, which is an extension of a branchedauxiliary capacitance signal line CSL2 in the column 214 x.

As discussed above, the voltage signals VCS1 and VCS 2 are supplied tothe auxiliary capacitance lines CS1 and CS2 such that the phase of thepotential of the auxiliary capacitance line CS1 is opposite the phase ofthe potential of the auxiliary capacitance line CS2. As the phase of thepotential of the auxiliary capacitance line CS1 is opposite the phase ofthe potential of the auxiliary capacitance line CS2, there is adifference between the effective voltage applied to the sub-pixel PIX1and that for the sub-pixel PIX2 such that brightness varies among thesub-pixels PIX1 and PIX2. FIG. 28 is a timing chart showing drivewaveforms for pixels PIX. FIG. 28 shows an example where a positive datasignal is supplied to a source line 155.

Referring to FIG. 28, from time t0 onward, voltage signals VCS1 and VSC2are supplied to the auxiliary capacitance lines CS1 and CS2. In theperiod from time t1 to t2, the gate driver 11 drives the gate line 13G:GL(n), turning on the switching elements T1 and T2 such that a positivedata signal is supplied to the source line 155. This causes thepotentials of the sub-pixels PIX1 and PIX2 to rise. Then, at time t2, atwhich the switching element T1 is turned off, an H level voltage signalVCS1 is supplied to the auxiliary capacitance line CS1 such that thepotential of the sub-pixel PIX1 increases due to a voltage upthrust bythe capacitor Ccsl. On the other hand, at time t2, at which theswitching element T2 is turned off, an L level voltage signal VCS2 issupplied to the auxiliary capacitance line CS2 such that the potentialof the sub-pixel PIX2 decreases due to a voltage downthrust by thecapacitor Ccs2. From t2 onward, the gate line 13G is in a floating statesuch that the potentials of the sub-pixels PIX1 and PIX2 increase ordecrease depending on the voltage signals VCS1 and VCS2.

Thus, the sub-pixel PIX1 displays images in a luminance that is higherthan that determined by data signals, while the sub-pixel PIX2 displaysimages in a luminance that is lower than that determined by datasignals. As images of two different luminance levels are displayed inone pixel, the viewing angle dependency in y-characteristics is reduced.Further, as the gate drivers 11 are provided in the display region andthe auxiliary capacitance signal lines CSL1 and CSL2 for supplyingvoltage signals to the auxiliary capacitance lines CS1 and CS2 areprovided in the display region, the picture frame width is reduced.

Tenth Embodiment

The above ninth embodiment describes an implementation where theauxiliary capacitance signal line CSL1 and CSL2 are provided in theregion of pixels to serve as auxiliary capacitance control elements andthe potentials of the auxiliary capacitance lines CS1 and CS2 arecontrolled depending on the vehicle signals supplied to the auxiliarycapacitance signal lines CSL1 and CSL2. The present embodiment describesan implementation where CS drivers for controlling the potentials of theauxiliary capacitance lines CS1 and CS2 are provided in the region ofpixels to serve as auxiliary capacitance control elements.

FIG. 29 shows an equivalent circuit of a pixel according to the presentembodiment. In FIG. 29, the components that are the same as thecorresponding ones of the ninth embodiment are labeled with the samereference numerals as in the ninth embodiment. The differences from theninth embodiment will be described below. As shown in FIG. 29, noauxiliary capacitance signal lines CSL1 and CSL2 as discussed above areconnected with the auxiliary capacitance lines CS1 and CS2.

The construction of the CS drivers will be described below. FIG. 30shows an equivalent circuit of a CS driver according to the presentembodiment. This implementation is a CS driver 80 for controlling thepotential of an auxiliary capacitance line CS1(n). As shown in FIG. 30,the CS driver 80 includes TFT-a to -j, TFT-k1 and TFT-k2, eachconstituted by a thin-film transistor, and a capacitor cbst. Thearrangement with the TFT-a to -j and capacitor cbst is the same as thearrangement of the gate driver 11 with the TFT-A to -J and capacitorCbst except that different clock signals (CRC and CRD) are supplied.

In this implementation, the potential of the gate line 13G: GL(n+1) issupplied to the gate terminal and drain terminal of the TFT-b and thegate terminal of the TFT-j. A clock signal (CKC) is supplied to the gateterminal of the TFT-h and the drain terminal of the TFT-f. A clocksignal (CKD) is supplied to the gate terminals of the TFT-d and -g. Theclock signals (CKC) and (CRD) are two-phase clock signals whose phase isreversed at each horizontal scan interval (see FIG. 31). The clocksignal (CKC) has the same phase as the clock signal (CKB), while theclock signal (CRD) has the same phase as the clock signal (CKA).

The TFT elements of the CS driver 80 to which the clock signals (CRC,CRD), power supply voltage signal (VSS) and reset signal (CLR) aresupplied, shown in FIG. 30, are connected with the control circuit (notshown) provided in the source driver 3 (not shown) via lines 15L1 formedby the source line layer 15.

In FIG. 30, the line connected with the source terminal of the TFT-b,the drain terminal of the TFT-a, the source terminal of the TFT-c, oneelectrode of the capacitor cbst and the gate terminal of the TFT-f willbe referred to as netC. The line connected with the gate terminal of theTFT-c, the source terminal of the TFT-g, the drain terminal of theTFT-h, the source terminal of the TFT-i and the source terminal of theTFT-j will be referred to as netD. The line connected with the otherelectrode of the capacitor cbst, the source terminal of the TFT-f andthe drain terminals of the TFT-e and TFT-d will be referred to as lineCL(n).

Further, the CS driver 80 includes a TFT-k1 and TFT-k2 each having agate terminal connected with the line CL(n). The source terminal of theTFT-k1 is connected with the auxiliary capacitance line CS1. The voltagesignal VCS1 or VCS2 is supplied to the drain terminal of the TFT-k1 fromthe control circuit (not shown) provided along the same side of thedisplay device as the source driver 3 (not shown). The source terminalof the TFT-k2 is connected with the auxiliary capacitance line CS2. Thevoltage signal VCS1 or VCS2 is supplied to the drain terminal of theTFT-k2 from the control circuit (not shown). As is the case in the aboveninth embodiment, the voltage signals VCS1 and VCS2 are signals withpotentials of opposite phases, and the polarity of each of them isreversed on a frame-to-frame basis by the control circuit (not shown).

When the line CL(n) goes to H level, the TFT-k1 and TFT-k2 turn on.Then, the potential of the voltage signal VCS1 supplied to the TFT-k1and TFT-k2 is supplied to the auxiliary capacitance lines CS1(n) andCS1(n+1). Further, the potential of the voltage signal VCS2 supplied tothe TFT-k1 and TFT-k2 is supplied to the auxiliary capacitance linesCS2(n) and CS2(n+1).

The elements constituting the above CS driver 80 are located in pixelregions where no gate driver 11 is present. FIGS. 31A and 31B show anexample arrangement of the CS driver 80. The representations of FIGS.31A and 31B are connected at the column 200 x and are continuous.

Although FIGS. 31A and 31B do not have the character “TFT-”, “a” to “k2”in FIGS. 31A and 31B indicate TFT-a to TFT-k2 constituting parts of CSdrivers 80. As shown in this implementation, the elements of a CS driver80 are dispersed in pixel regions in the same row. Lines 15L1 areprovided in the pixel regions of the columns in which TFT elements(TFT-a and c to j) of the CS drivers 80 to which the clock signals (CRC,CRD), power supply voltage signal (VSS) and reset signal (CLR) aresupplied are provided. Further, auxiliary capacitance signal lines CSL1and CSL2 are provided in the pixel regions of the columns in which theTFT elements (TFT-k1 and k2) to which the voltage signals VCS1 and VCS2are supplied are provided. The CS drivers 80 in a row and those in anadjacent row are arranged such that the clock signals and voltagesignals supplied to the former have a phase opposite to that for thelatter.

The operation of the CS driver 80 will be described below. FIG. 32 is atiming chart showing the operation of the CS driver 80. FIG. 32 shows anexample where the auxiliary capacitance line CS1 is driven; the samewill apply to the auxiliary capacitance line CS2. In FIG. 32, the periodbetween t2 and t3 is the period during which the gate line 13G: GL(n+1)is selected. The control circuit (not shown) supplies the clock signal(CRC) and clock signal (CRD) to the CS driver 80. The phase of each ofthe clock signal (CRC) and clock signal (CRD) is reversed at eachhorizontal scan interval. Although not shown in FIG. 32, a reset signal(CLR) that goes to H (high) level at each vertical scan interval andremains that way for a predetermined period of time is supplied to theCS driver 80 from the control circuit (not shown). When the reset signal(CLR) is supplied, the netC, netD and gate line 13G transitions to L(low) level.

Between time t0 to t1, an L level clock signal (CRC) is supplied and anH level clock signal (CRD) is supplied, which turns on the TFT-g andturns off the TFT-h, charging the netD to H level. Further, the TFT-cand TFT-d turn on and the TFT-f turns off, charging the netC to an Llevel power supply voltage (VSS) such that an L level potential isprovided to the line CL(n).

Next, at time t1, the clock signal (CRC) goes to H level and the clocksignal (CRD) goes to L level, which turns off the TFT-g and turns on theTFT-h, charging the netC to L level. Further, the TFT-c and TFT-d turnoff such that the potential of the netC is maintained at L level and anL level potential is provided to the line CL(n).

At time t2, the clock signal (CRC) goes to L level and the clock signal(CRD) goes to H level and the set signal (S) is supplied to the CSdriver 80 via the gate line 13G: GL(n+1), which turns on the TFT-b andcharges the netC to H level. Further, the TFT-j turns on and TFT-g turnson and the TFT-h turns off such that the netD is maintained at L level.The TFT-c and TFT-f turn off such that the potential of the netC doesnot decrease and is maintained. Meanwhile, the TFT-d is on such that anL level potential is provided to the line CL(n).

At time t3, the clock signal (CRC) goes to H level and the clock signal(CRD) goes to L level, which turns on the TFT-f and turns off the TFT-d.As the potential of the drain terminal of the TFT-f increases, thecapacitor Cbst connected with the netC charges the netC to a potentialhigher than the H level of the clock signal (CRC). Meanwhile, the TFT-gand TFT-j are off and TFT-h is on such that the potential of the netD ismaintained at L level. The TFT-c is off such that the potential of thenetC does not decrease, and the H level potential of the clock signal(CRC) is provided to the line CL(n) and the TFT-k1 and TFT-k2 turn on.When the TFT-k1 and TFT-k2 are on, the potential of the voltage signalVCS1 being supplied to the TFT-k1 and TFT-k2 is provided to theauxiliary capacitance line CS1.

At time t4, the clock signal (CRC) goes to L level and the clock signal(CRD) goes to H level, which turns on the TFT-g and turns off the TFT-h,charging the netD to H level. This turns on the TFT-c and charges thenetC to L level. Meanwhile, the TFT-d is on and the TFT-f is off suchthat an L level potential is provided to the line CL(n) and the TFT-k1and TFT-k2 turn off. The capacitor Ccs1 connected with the auxiliarycapacitance line CS1 maintains the potential of the auxiliarycapacitance line CS1 at H level.

FIG. 33A shows a timing chart showing the operation of the gate driver11 and the operation of the CS driver 80. In this implementation, duringthe mth frame, an L level voltage signal VCS2 and an H level voltagesignal VCS1 are supplied. As shown in FIG. 33A, during the mth frame,the gate lines 13G: GL(n−1) to GL(n+1) are sequentially driven by thegate drivers 11 in response to the clock signals (CKA and CKB). Each ofthe potentials of the lines CL(n−1) to CL(n) in the CS drivers 80transitions to H level, in response to the clock signal (CKC or CRD),after the gate line 13G of the subsequent row is driven. The voltagesignal VCS2 is supplied to the TFT-k1 and k2 connected with the lineCL(n−1). Thus, when the line CL(n−1) goes to H level during the mthframe, the L level potential of the voltage signal VCS2 is supplied tothe auxiliary capacitance line CS1(n−1).

Further, as shown in FIG. 31b , the voltage signal VCS1 is supplied tothe TFT-k1 and k2 connected with the line CL(n). Thus, when the lineCL(n) goes to H level, the H level potential of the voltage signal VCS1is supplied to the auxiliary capacitance line CS(n). The same applies tothe TFT-k1 and k2 connected with the line CL(n+1): when the L levelvoltage signal VCS2 is supplied, an L level potential is supplied to theauxiliary capacitance line CS1(n+1).

During the m+1th frame, the polarities of the voltage signals VCS1 andVCS2 are reversed such that an H level voltage signal VCS2 and an Llevel voltage signal VCS1 are supplied. Thus, the potentials supplied tothe auxiliary capacitance lines CS1(n−1) to CS1(n+1) are the reversedones with respect to those of the mth frame.

Thus, as shown in FIG. 33B, at time t1, the gate line 13G: GL(n) isdriven, which turns on the switching elements T1 and T2 of thesub-pixels PIX1(n) and PIX2(n) such that a positive data signal issupplied to the source lines 155. At the same time, the potentials ofthe sub-pixels PIX1(n) and PIX2(n) increase.

Then, at time t2, the potential of the gate line 13G: GL(n) transitionsfrom H level to L level, which causes the line CL(n−1) of the CS driver80 to transition from L level to H level. Then, at time t2, an L levelvoltage signal VCS2 is supplied to the auxiliary capacitance lineCS2(n), causing the potential of the sub-pixel PIX2(n) to decrease viathe capacitance Ccs2. On the other hand, at time t2, the gate line 13G:GL(n+1) is driven, and, at time t3, the potential of the gate line 13G:GL(n+1) transitions from H level to L level, which causes the line CL(n)of the CS driver 80 transitions to H level. Then, at time t3, an H levelvoltage signal VCS1 is supplied to the auxiliary capacitance lineCS1(n), causing the potential of the sub-pixel PIX1(n) to increase viathe capacitor Ccs1. Thus, the sub-pixel PIX1(n) displays an image at aluminance higher than that for data signals, while the sub-pixel PIX2(n)displays an image at a luminance lower than that for data signals.

Eleventh Embodiment

The present embodiment describes an implementation where viewing anglecharacteristics are improved by a method different from those of theninth and tenth embodiments when the display mode of the liquid crystaldisplay device 1 is the VA mode.

FIG. 34 shows an equivalent circuit of a pixel PIX according to thepresent embodiment. In FIG. 34, the components that are the same as thecorresponding ones of the tenth embodiment are labeled with the samereference characters as in the tenth embodiment. The differences fromthe above embodiments will be described below.

As shown in FIG. 34, the gate terminals of the switching elements T1 andT2 of the sub-pixels PIX1(n) and PIX2(n) of the pixel PIX are connectedwith the gate line 13G: GLa(n). In the present embodiment, the sub-pixelPIX1(n) has no capacitance C, and includes a liquid crystal capacitanceLC1 provided between the pixel electrode 17 a and common electrode (notshown).

A capacitor Ccs is provided in the sub-pixel PIX2. One of the electrodesof the capacitor Ccs is connected with an auxiliary capacitance line CSextending substantially parallel to the gate line 13G. The otherelectrode of the capacitor Ccs is connected with a switching element T3formed by a thin-film transistor. The gate terminal of the switchingelement T3 is connected with a gate line 13G: GLb(n) (hereinafterreferred to as sub-gate line) extending substantially parallel to thegate line 13G: GLa(n). The switching element T3 has a source terminalconnected with the pixel electrode 17 b and a drain terminal connectedwith the other electrode of the capacitor Ccs. The sub-pixel PIX2(n)includes a liquid crystal capacitance LC2 constituted by the pixelelectrode 17 b and the common electrode (not shown), and an auxiliarycapacitance constituted by the capacitor Ccs.

Thus, in the present embodiment, the sub-gate line 13G: GLb(n) islocated closer to the sub-pixel PIX2(n) than to the gate line 13G:GLa(n) between the sub-pixels PIX1(n) and PIX2(n). Each of the gate line13G: GLa(n) and sub-gate line 13G: GLb(n) is driven by the associatedgate driver 11 provided in the display region. Further, a potential witha polarity opposite that of gate signals supplied to the source lines15S is applied to the auxiliary capacitance line CS by the auxiliarycapacitance control circuit (not shown).

FIGS. 35A and 35B show an example arrangement of a gate driver 11 fordriving the gate line 13G: GLa(n) (hereinafter referred to as gatedriver 11_A) in the display region. FIGS. 36A and 36B show an examplearrangement of gate drivers 11 for driving the sub-gate lines 13G:GLb(n) (hereinafter referred to as gate driver 11_B) (i.e. sub-gate linedriver) in the display region.

The representations of FIGS. 35A and 35B are connected at the pixelregions of the column 200 x shown in these drawings and are continuous.The representations of FIGS. 36A and 36B are connected at the pixelregions of the column 201 x shown in these drawings and are continuous.Although FIGS. 35A and 35B and FIGS. 36A and 36B do not have thecharacter “TFT”, “A” to “J” in these drawings indicate “TFT-A” to“TFT-J”.

The elements constituting the gate driver 11_A (TFT-A to J and Cbst) aredispersed among gate lines 13G: GLa in FIGS. 35A and 35B. The TFT-B, Dto F and J of the gate driver 11_1A are connected with the gate lines13G: GLa. The gate lines 13G: GLa are sequentially driven by the gatedrivers 11_A in response to the control signals (CKA, CKB, CLR, and VSS)supplied via lines 15L1.

In FIGS. 36A and 36B, the elements constituting the gate driver 11_B(TFT-A to J and Cbst) are dispersed among gate lines 13G: GLa in columnsin which no gate driver 11_A is present. The TFT-B, D to F and J of thegate driver 11_B are connected with gate lines 13G: GLb. The gate lines13G: GLb are sequentially driven by the gate drivers 11_B in response tothe control signals (CKA, CKB, CLR, and VSS) supplied via lines 15L1.

FIG. 37 is a timing chart showing signals encountered when thesub-pixels PIX1(n) and PIX2(n) are driven. As shown in FIG. 37, at timet1, the gate driver 11_A causes the potential of the gate line 13G:GLa(n) to transition to H level, turning on the switching elements T1and T2. Then, when a positive data signal is supplied to the source line15S, the potentials of the sub-pixels PIX1(n) and PIX2(n) increasedepending on the voltage of data signals such that data is written tothe sub-pixels PIX1(n) and sub-pixels PIX2(n).

At time t2, the potential of the gate line 13G: GLa(n) transitions to Llevel and, then, at time t3, the gate driver 11_B causes the potentialof the sub-gate line 13G: GLb(n) to transition to H level. The switchingelement T1 is off, which maintains the potential of the sub-pixelPIX1(n) and causes the sub-pixel PIX1(n) to display an image at the sameluminance as that determined by data signals. On the other hand, theswitching element T3 is on, which re-distributes electric charge untilone terminal of the capacitor Ccs (Va) and the pixel electrode 17 b goto the same potential. Thus, the potential of the sub-pixel PIX2(n)decreases such that an image is displayed at a luminance lower than thatdetermined by data signals.

Twelfth Embodiment

The present embodiment describes an implementation where viewing anglecharacteristics are improved by a method different from those of thetenth and eleventh embodiments when the display mode of the liquidcrystal display device 1 is the VA mode. FIG. 38 shows an equivalentcircuit of a pixel PIX according to the present embodiment. As shown inFIG. 38, in the present embodiment, a gate line 13G: GL1(n) and a gateline 13G: GL2(n) (sub-gate line) are provided in the pixel PIX. The gateterminal of a switching element T1 connected with the pixel electrode 17a is connected with the gate line 13G: GL1(n). The gate terminal of aswitching element T2 connected with the pixel electrode 17 b isconnected with the gate line 13G: GL2(n). A capacitor C is connectedbetween the pixel electrode 17 a and pixel electrode 17 b. The gate line13G: GL1(n) and the gate line 13G: GL2(n) are driven by the associatedgate drivers (see FIG. 4) provided in the display region. The gatedriver 11 for driving the gate line 13G: GL1(n) will be hereinafterreferred to as gate driver 11_1 (i.e. driving circuit). The gate driver11 for driving the gate line 13G: GL2(n) will be hereinafter referred toas gate driver 11_2 (i.e. sub-gate line driver).

The gate drivers 11_1 and 11_2 have the same construction as the gatedriver 11 of the first embodiment except that the set signal (S)supplied to the terminals 111 and 112 and the scan signal (OUT) from theterminal 120 are provided to different destinations. In the gate driver11_1, a scan signal provided to the gate line 13G of the preceding rowGL2(n−1) is supplied as a set signal (S) to the terminals 111 and 112shown in FIG. 4. Then, the scan signal is provided to the gate line 13G:GL1(n) through the terminal 120 of FIG. 4. In the gate driver 11_2, ascan signal provided to the gate line 13G: GL1(n) is supplied as a setsignal (S) to the terminals 111 and 112 shown in FIG. 4. Then, the scansignal is provided to the gate line 13G: GL2(n) through the terminal 120shown in FIG. 4.

FIGS. 39A to 39D show an example arrangement of gate drivers 11_1 and11_2 in the display region. The pixel regions of FIGS. 39A to 39D form acontinuity. The representations of FIGS. 39A and 39B are connected atthe pixel regions of the column 200 x shown in these drawings and arecontinuous. The representations of FIGS. 39C and 39D are connected atthe pixel regions of the column 202 x shown in these drawings and arecontinuous.

Although FIGS. 39A to 39D do not have the character “TFT”, “A” to “J” inthese drawings indicate “TFT-A” to “TFT-J” constituting the gate drivers11. As shown in FIGS. 39A and 39B, the elements constituting the gatedrivers 11_1 (TFT-A to J and Cbst) are dispersed among gate lines 13G:GL1. The TFT-B and J of a gate driver 11_1 are connected with the gateline 13G: GL2 of the preceding row. The TFT-D to F and capacitor Cbst ofthe gate drivers 11_1 are connected with gate lines 13G: GL1. The gatelines 13G: GL1 are sequentially driven by the gate drivers 11_1 inresponse to the control signals (CKA, CKB, CLR and VSS) supplied via thelines 15L1.

As shown in FIGS. 39C and 39D, the elements constituting the gatedrivers 11_2 (TFT-A to J and Cbst) are dispersed among gate lines 13G:GL1 in the columns in which no gate driver 11_1 is present. The TFT-Band J of the gate drivers 11_2 are connected with gate lines 13G: GL1.Further, the TFT-D to F and capacitor Cbst of a gate driver 11_2 areconnected with the gate line 13G: GL2 of the subsequent row. The gatelines 13G: GL2 are sequentially driven by the gate drivers 11_2 inresponse to the control signals (CKA, CKB, CLR and VSS) supplied via thelines 15L1. That is, in the present embodiment, the gate line 13G:GL2(n−1) is driven and then the gate line 13G: GL1(n) is driven by gatedrivers 11_1. After the gate line 13G: GL1(n) is driven, the gate line13G: GL2(n) is driven by the gate driver 11_2.

FIG. 40 is a timing chart showing the driving of the gate lines 13G:GL1(n) and GL2(n) and changes in the potential of the pixel. As shown inFIG. 40, in the present embodiment, one horizontal interval is dividedinto a T1 period and T2 period, where the gate line 13G: GL1(n) isdriven in the period T1 and the gate line 13G: GL(2) is driven in the T2period.

At time t1, the gate line 13G: GL1(n) is driven by the gate driver 11_1and a positive data signal is supplied to the source line 15S, whichturns on the switching element T1. Thus, the potential of the sub-pixelPIX1 increases depending on the data signal. After time t2, thepotential of the gate line 13G: GL1(n) goes to L level and the gate line13G: GL2(n) is driven by the gate driver 11_2, which turns off theswitching element T1 and turns on the switching element T2. Thus, thepotential of the sub-pixel PIX2 increases depending on the data signal.At this moment, the potential of the sub-pixel PIX1 is in a floatingstate, which amplifies the potential of the sub-pixel PIX1 via thecapacitor C. As a result, the sub-pixel PIX2 displays an image at aluminance determined by data signals, while the sub-pixel PIX1 displaysan image at a luminance higher than that determined by data signals.

Thirteenth Embodiment

The present embodiment describes an implementation where, when thedisplay mode of the liquid crystal display device 1 is the VA mode, thepotential of an auxiliary capacitance provided in a pixel is controlledto reduce the voltage amplitude of data signals, thereby reducing powerconsumption.

FIG. 41 shows an equivalent circuit of a pixel PIX according to thepresent embodiment. As shown in FIG. 41, in the present embodiment, in apixel PIX are provided a switching element TFT-PIX connected with thegate line 13G: GL(n), a pixel electrode 17, a capacitor Ccs, and anauxiliary capacitance line CS(n) extending substantially parallel to thegate line 13G. One of the electrodes of the capacitor Ccs is connectedwith the pixel electrode 17, while the other electrode is connected withthe auxiliary capacitance line CS(n). The pixel PIX includes a liquidcrystal capacitance LC formed between the pixel electrode 17 and commonelectrode 18 (see FIG. 42), and an auxiliary capacitance formed by thecapacitor Ccs.

FIG. 42 is a schematic cross-sectional view of the display panel 2according to the present embodiment. As shown in FIG. 42, a liquidcrystal layer 30 is provided between the active-matrix substrate 20 aand counter-substrate 20 b. The counter-substrate 20 b includes a glasssubstrate 2 b, on which a common electrode 18 is provided. Further, theactive-matrix substrate 20 a includes a capacitor Ccs below the pixelelectrode 17, with the interlayer insulating film 24 being present inbetween. When no voltage is applied to the liquid crystal capacitance LCbetween the common electrode 18 and pixel electrode 17, the liquidcrystal molecules are vertically oriented, and the orientation of theliquid crystal molecules changes depending on the voltage applied. Inthe present embodiment, as is the case in the first embodiment, a gatedriver 11 provided in the display region drives a gate line 13G.Further, a CS driver provided in the display region (i.e. auxiliarycapacitance line driver) controls the potential of an auxiliarycapacitance line CS(n).

In the present embodiment, the elements constituting a gate driver 11and a CS driver are constructed as a single unit. FIG. 43 shows anequivalent circuit composed of the elements of a CS driver and gatedriver 11. The TFT-A to J and capacitor Cbst of FIG. 43 have the sameconstruction as the gate driver 11 of the first embodiment. In FIG. 43,the line to which the electrode of the capacitor Cbst that is notconnected with the netA, the source terminal of the TFT-F, and the drainterminals of the TFT-E and TFT-D are connected will be referred to asline CL(n). The line CL(n) is connected with the gate line 13G: GL(n+1).

The line CL(n) of the gate driver 11 is connected with the gate terminalof the TFT-K. The TFT-K is a switching element constituting a part ofthe CS driver. The voltage signal VCS1 or VCS2 is supplied to the sourceterminal of the TFT-K, and the drain terminal is connected with theauxiliary capacitance line CS(n).

As is the case with the first embodiment, a set signal (S) is suppliedto the TFT-B and J of the gate driver 11 for driving the gate line 13G:GL(n+1) by the gate line 13G of the preceding row (GL(n)). In responseto the control signals (CKA, CKB, CLR, VSS), the potential of the lineCL(n) is provided to the gate line 13G: GL(n+1). When the potential ofthe line CL(n) transitions to H level, the TFT-K turns on, and thepotential of the voltage signal VCS1 or VCS2 is supplied to theauxiliary capacitance line CS(n). The phases of the potentials of thevoltage signals VCS1 and VCS2 are opposite to each other, and thesevoltage signals are supplied by the control circuit (not shown) whilethe polarity of each of them is reversed on a frame-to-frame basis.

FIGS. 44A and 44B show an example arrangement of the elements of FIG. 43in the display region. The representations of FIGS. 44A and 44B areconnected at the column 200 x in these drawings and are continuous. Asshown in FIGS. 44A and 44B, auxiliary capacitance lines CS are providedto extend substantially parallel to the gate lines 13G. Although FIGS.44A and 44B do not have the character “TFT-”, “A” to “K” in thesedrawings indicate TFT-A to TFT-K. As shown in these drawings, the TFT-Ato J, capacitor Cbst, TFT-K are dispersed among pixel regions betweengate lines 13G. Further, the gate terminals of the TFT-B and J of thegate driver 11 for driving the gate line 13G: GL(n), for example, areconnected with the gate line 13G: GL(n−1). The source terminals of theTFT-D to F and one of the electrodes of the capacitor Cbst are connectedwith the gate line 13G: GL(n).

In the pixel regions of the columns in which TFTs-K are provided in FIG.44B, auxiliary capacitance signal lines VCSL1 and VCSL2 for supplyingvoltage signals VCS1 or VCS2 are provided to extend substantiallyparallel to the source lines 15S. The gate terminal of a TFT-K and thesource terminal of a TFT-F are connected via a line CL(n). The drainterminal of a TFT-K is connected with an auxiliary capacitance line CS.Each TFT-K is disposed so as to have a potential with the phase that isopposite that of the potential of voltage signals supplied to the TFT-Kin an adjacent row.

The operation of the gate driver 11 and CS driver represented by theequivalent circuit of FIG. 43 will be described below. FIG. 45 is atiming chart showing the operation of the equivalent circuit of FIG. 43.FIG. 45 shows an implementation where the gate line 13G: GL(n+1) isdriven by the gate driver 11. The operation of the gate driver 11driving the gate line 13G is the same as the operation illustrated byFIG. 9 (for an implementation where the gate line 13G: GL(n) is driven),and thus its description will not be given.

At time t3 of FIG. 45, the potential of the netA is further amplifiedand an H level potential is supplied to the line CL(n), i.e. the gateline 13G: GL(n+1), which turns on the TFT-K. Thus, the potential of thevoltage signal VCS1 supplied to the TFT-K is provided to the auxiliarycapacitance line CS(n). In this example, an H level voltage signal VCS1is supplied. In response to the voltage signal VCS1, the potential ofthe auxiliary capacitance line CS(n) transitions from L level to Hlevel.

That is, as shown in FIG. 46, the gate lines 13G: GL(n−1) to GL(n) aresequentially driven, and the potential of the corresponding line CLtransitions from L level to H level at the time point at which the gateline 13G of the subsequent row is driven. In FIG. 46, if an H levelvoltage signal VCS1 and L level voltage signal VCS2 are provided by thecontrol circuit (not shown) in the mth frame, an L level voltage signalVCS1 and an H level voltage signal VCS2 are provided by the controlcircuit (not shown) in the m+1th frame.

As shown in FIGS. 44A and 44B, the voltage signal VCS2 is supplied tothe TFT-K connected with the auxiliary capacitance line CS(n−1) andauxiliary capacitance line CS(n+1). Further, the voltage signal VCS1 issupplied to the TFT-K connected with the auxiliary capacitance lineCS(n). Thus, the potential of the auxiliary capacitance line CS(n−1) ismaintained at H level by the voltage signal VCS2 supplied in the m−1thframe until the gate line 13G: GL(n) is driven. Then, it is caused totransition to L level by the voltage signal VCS2 of the mth frame at thetime point at which the gate line 13G: GL(n) is driven, that is, whenthe potential of the line CL(n−1) goes to H level.

Further, until the gate line 13G: GL(n+1) is driven, the potential ofthe auxiliary capacitance line CS(n) is maintained at L level by thevoltage signal VCS1 supplied in the m−1th frame. Then, it is caused totransition to H level by the voltage signal VSC1 of the mth frame at thetime point at which the gate line 13G: GL(n+1) is driven, that is, whenthe potential of the line CL(n) goes to H level. Similarly, when thepotential of the line CL(n+1) goes to H level, the voltage signal VCS2of the mth frame causes the potential of the auxiliary capacitance lineCS(n+1) to transition to L level.

In the m+1th frame, each of the potentials of the voltage signals VCS1and VCS2 of the mth frame is reversed, and a potential with the reversedpolarity with respect to the polarity of the potentials of the mth frameis supplied to the auxiliary capacitance lines CS(n−1) to CS(n+1).

Thus, when the gate line 13G: GL(n) is driven in the mth frame, thepotential of the pixel PIX(n) having the pixel electrode 17 connectedwith the gate line 13G: GL(n) increases depending on the data signal.Then, when the gate line 13G: GL(n+1) is driven and the auxiliarycapacitance line CS(n) goes to H level, the potential of the pixelPIX(n) is amplified via the capacitor Ccs. In the m+1th frame, anegative data signal is supplied to the source line 15S and an L levelvoltage signal VCS1 is supplied to the auxiliary capacitance line CS(n)via the auxiliary capacitance signal line VCSL1. As a result, when thegate line 13G: GL(n) is driven, the potential of the pixel PIX(n) isnegatively amplified in response to the data signal, and, when the gateline 13G: GL(n+1) is driven and the auxiliary capacitance line CS(n)goes to H level, it is negatively amplified via the capacitor Ccs.

Thus, the pixel PIX(n) displays an image at a luminance that is higherthan that determined by a data signal supplied in the mth frame. Thisreduces the amplitude of data signals, reducing power consumption.Further, in the present embodiment, an element (TFT-K) constituting apart of a CS driver controlling the potential of an auxiliarycapacitance line CS, together with the gate driver 11, is provided inthe display region, and the voltage signals VCS1 and VCS2 are suppliedto the CS driver from the source driver 3 via the auxiliary capacitancesignal lines VCSL1 and VCSL2. This reduces the width of the portions ofthe picture frame that are along the side without a source driver 3compared with implementation where CS drivers are provided outside thedisplay region.

Fourteenth Embodiment

The present embodiment describes an implementation where, when thedisplay mode of the liquid crystal display device 1 is the fringe fieldswitching (FFS) mode, the potential of the common electrode iscontrolled to reduce the amplitude of the voltage of data signals,thereby reducing power consumption.

FIG. 47 shows an equivalent circuit of a pixel PIX according to thepresent embodiment. As shown in FIG. 47, in the pixel PIX are provided aTFT-PIX connected with the gate line 13G: GL(n), a pixel electrode 17, acapacitor C, and a common electrode line 18L (COM(n)) extendingsubstantially parallel to the gate line 13G. The capacitor C has oneelectrode connected with the pixel electrode 17 and the other electrodeconnected with the common electrode line 18L: COM(n). The pixel PIXincludes a liquid crystal capacitance LC formed by the pixel electrode17 and common electrode line 18L, and an auxiliary capacitance formed bya capacitor C.

FIG. 48 is a schematic cross-sectional view of the display panel 2 ofthe present embodiment. As shown in FIG. 48, a liquid crystal layer 30is provided between an active-matrix substrate 20 a and acounter-substrate 20 b. A comb teeth-shaped pixel electrode 17 isprovided on the active-matrix substrate 20 a. A common electrode line18L is provided below the pixel electrode 17, with the interlayerinsulating film 24 being present in between. When no voltage is appliedbetween the common electrode line 18L and pixel electrode 17, the liquidcrystal molecules are horizontally oriented, and the orientation ofliquid crystal molecules changes depending on the voltage applied.

As is the case in the first embodiment, in the present embodiment, agate driver 11 provided in the display region drives a gate line 13G,and, a COM driver (i.e. common electrode driver) provided in the displayregion controls the potential of the common electrode line 18L. Thepolarity of the potential of the common electrode line 18L is reversedon a frame-to-frame basis. A data signal with a polarity reversed withrespect to the potential of the common electrode line 18L is supplied tothe source line 15S on a frame-to-frame basis.

In the present embodiment, the elements constituting a gate driver 11and COM driver are constructed as a single unit. FIG. 49 shows anequivalent circuit composed of the elements of a COM driver and gatedriver 11. The equivalent circuit of FIG. 49 has the same constructionas the equivalent circuit of FIG. 43 for the thirteenth embodimentexcept that the gate line 13G: GL(n−1) is driven and the source terminalof the TFT-K is connected with the common electrode line 18L: COM(n). Inthe present embodiment, the TFT-K is a switching element constituting apart of the COM driver. The potentials of the voltage signals V1 and V2supplied to the drain terminal of the TFT-K are of opposite phases. Thepolarity of each of the voltage signals V1 and V2 is reversed by thecontrol circuit (not shown) on a frame-to-frame basis.

FIGS. 50A and 50B show an example arrangement of the elementsconstituting the equivalent circuit of FIG. 49 in the display region.The representations of FIGS. 50A and 50b are connected at the column 200x in these drawings and are continuous. As shown in FIGS. 50A and 50B,common electrode lines 18L extend substantially parallel to the gatelines 13G. Although FIGS. 50A and 50B do not have the character “TFT-”,“A” to “K” in these drawings indicate TFT-A to TFT-K described above.The TFT-A to J, capacitor Cbst, TFT-K are dispersed among pixel regionsbetween gate lines 13G. The gate terminals of the TFT-B and J of thegate driver 11 for driving the gate line 13G: GL(n−1) is connected withthe gate line 13G of the preceding row GL(n−2), and the source terminalof the TFT-D to F and one of the electrodes of the capacitor Cbst areconnected with the gate line 13G: GL(n−1).

In the pixel regions of the columns in which the TFTs-K are provided inFIG. 50B, common electrode signal lines VL1 and VL2 each supplying thevoltage signal V1 or V2 are provided to extend substantially parallel tothe source lines 15S. The source terminal of the TFT-F of the gatedriver 11 for driving the gate line 13G: GL(n−1) is connected with thegate terminal of the TFT-K via the line CL(n). The source terminal ofthe TFT-K is connected with the common electrode line 18L: COM(n). TheTFTs-K in a row and those in an adjacent row are arranged such that thevoltage signals and potentials supplied to the former have a phaseopposite to that for the latter.

The operation of the gate driver 11 and COM driver will be describedbelow. FIG. 51 is a timing chart showing the operation of the equivalentcircuit of FIG. 49. FIG. 51 shows an example where the gate line 13G:GL(n+1) is driven by the gate driver 11. The operation of the gatedriver 11 driving the gate line 13G is the same as the operationillustrated by FIG. 9 (for an example where the gate line 13G: GL(n) isdriven), and thus their description will not be given.

At time t3 of FIG. 51, the potential of the netA is further amplified asthe clock signal (CKA) transitions to H level, and an H level potentialis provided to the line CL(n), i.e. the gate line 13G: GL(n−1), whichturns on the TFT-K. Thus, the potential of the voltage signal V1supplied to the TFT-K is provided to the common electrode line 18L:COM(n). In this example, an H level voltage signal V1 is supplied. Thepotential of the common electrode line 18L: COM(n) transitions from Llevel to H level. After the common electrode line 18L: COM(n)transitions to H level, the gate line 13G: GL(n) is driven in a mannersimilar to that in which the gate line 13G: GL(n−1) is driven.

That is, as shown in FIG. 52, the gate lines 13G: GL(n−1) to GL(n+1) aresequentially driven, and the potential of each of the lines CL(n−1) toCL(n+1) sequentially transitions from L level to H level at the timepoint at which the gate line 13G of the preceding row is driven. In FIG.52, an H level voltage signal V1 and an L level voltage signal V2 areprovided by the control circuit (not shown) in the mth frame. In them+1th frame, an L level voltage signal V1 and an H level voltage signalV2 are provided by the control circuit (not shown).

The voltage signal V1 is supplied to the TFT-K connected with the commonelectrode line 18L: COM(n), and the voltage signal V2 is supplied to theTFT-K connected with the common electrode line 18L: COM(n+1) (see FIGS.50A and 50B). Thus, the potential of the common electrode line 18L:COM(n) is maintained at L level by the voltage signal V1 supplied in them−1th frame until the gate line 13G: GL(n−1) is driven. Then, it iscaused to transition to H level by the voltage signal V1 of the mthframe at the time point at which the gate line 13G: GL(n−1) is driven,that is, when the potential of the line CL(n) goes to H level.Similarly, the potential of the common electrode line 18L: COM(n−1) iscaused to transition to L level by the voltage signal V2 of the mthframe at the time point at which the gate line 13G: GL(n−2) is driven,that is, when the potential of the line CL(n−1) goes to H level.

In the m+1th frame, the polarity of each of the voltage signals V1 andV2 is reversed with respect to those of the mth frame such thatpotentials with polarities reversed with respect to those for the mstframe are supplied to the common electrode lines 18L: COM(n−1) toCOM(n+1). The polarity of the potential of the common electrode line 18Lof each pixel PIX is reversed before the data for this pixel PIX iswritten such that a data signal with a polarity opposite to that for thecommon electrode lines 18L is provided by the source driver 3 to thesource lines 155. Thus, when a negative data signal is written to thepixel PIX (n) in the mth frame, as shown in FIG. 52, the potential ofthe line CL(n) goes to H level, and, when the potential of the commonelectrode line 18L: COM(n) transitions to H level, the potential of thepixel PIX(n) is positively amplified. Then, the gate line 13G: GL(n) isdriven and a negative data signal is supplied to the source line 155.Thus, the potential of the pixel PIX(n) is negatively amplifieddepending on the data signal and the potential of the common electrodeline 18L: COM(n), and is maintained until the m+1th frame.

In the m+1th frame, when the potential of the common electrode line 18L:COM(n) transitions from H level to L level, the potential of the pixelPIX(n) is negatively amplified. Then, the gate line 13G: GL(n) is drivenand a positive data signal is supplied to the source line 15S. Thus, thepotential of the pixel PIX(n) is positively amplified depending on thedata signal and the potential of the common electrode line 18L: COM(n),and is maintained until the m+2th frame.

As the polarity of a data signal is reversed in response to the commonelectrode line 18L whose polarity is reversed on a frame-to-frame basis,the amplitude of a data signal is reduced compared with that inimplementations where the potential of the common electrode line 18L isconstant, thereby reducing power consumption. Further, providing in thedisplay region the elements constituting a COM driver for controllingthe potential of a common electrode line 18L, together with a gatedriver 11, reduces the width of the portions of the picture frame thatare along the three sides of the display device, i.e. the sides otherthan that one having the source driver 3.

Fifteenth Embodiment

The fourteenth embodiment describes an implementation where theorientation of liquid crystal molecules is controlled by a horizontalelectric field produced by the pixel electrodes and common electrode.The present embodiment describes an implementation where the orientationof liquid crystal molecules is controlled using a vertical electricfield and horizontal electric field to improve the response speed ofliquid crystal molecules.

FIG. 53 shows an equivalent circuit of a pixel according to the presentembodiment. FIG. 54 is a schematic cross-sectional view of the pixel ofFIG. 53. The construction of the display panel 2 and the pixel accordingto the present embodiment will be described below with reference toFIGS. 53 and 54.

As shown in FIG. 53, the pixel PIX of the present embodiment includes aTFT-PIX connected with a gate line 13G and a source line 15S, a pixelelectrode 17, a common electrode 18 and a capacitor C. Further, a commonelectrode line 18L is provided for the pixel PIX, extendingsubstantially parallel to the gate line 13G. The drain terminal of theTFT-PIX is connected with the pixel electrode 17 and one of theelectrodes of the capacitor C. The other electrode of the capacitor C isconnected with the common electrode line 18L.

As shown in FIG. 54, the counter-substrate 20 b includes a glasssubstrate 2 b, a counter-electrode 181 provided on the glass substrate,and a black matrix and color filters (both not shown). An overcoat layer19 is provided on top of the counter-electrode 181. The active-matrixsubstrate 20 a includes a pixel electrode 17 and a common electrode 18disposed in parallel, and an interlayer insulating film 24 is providedbelow the pixel electrode 17 and common electrode 18. A common electrodeline 18L is provided below the interlayer insulating film 24, and thecommon electrode line 18L and common electrode 18 are connected witheach other via a contact hole formed in the interlayer insulating film24.

The pixel PIX includes liquid crystal capacitances CLC1, CLC2 a and CLS2b. The liquid crystal capacitance CLC1 is provided between the pixelelectrode 17 and common electrode 18. The liquid crystal capacitanceCLC2 a is provided between the counter-electrode 181 and pixel electrode17. The liquid crystal capacitance CLC2 b is provided between the commonelectrode 18 and common electrode line 18L and the counter-electrode181. The liquid crystal capacitance CLC1 produces a horizontal electricfield and the liquid crystal capacitance CLC2 a and liquid crystalcapacitance CLC2 b produce a vertical electric field.

The potentials of the common electrode 18 and common electrode line 18Lare controlled by a COM driver (i.e. common electrode driver), describedbelow, such that their polarity is reversed on a frame-to-frame basis.Further, a data signal with a reversed polarity with respect to thepotential of the common electrode 18 and common electrode line 18L issupplied by the source driver 3 to the source line 15S.

When a positive data signal is written to the pixel, for example, a DCvoltage of 7.5 volts may be applied to the counter-electrode 181 and avoltage of 15 volts may be applied to the pixel electrode 17 and thecommon electrode 18 and common electrode line 18L, in which case nohorizontal electric field is produced between the pixel electrode 17 andcommon electrode 18. As a result, as shown in FIG. 55A, liquid crystalmolecules 301 are vertically oriented. Pixels oriented in this mannerdisplay black. On the other hand, under the above condition, a voltageof 0 volts on the pixel electrode 17 produces a horizontal electricfield between the pixel electrode 17 and common electrode 18. In thiscase, as shown in FIG. 55B, the orientation of liquid crystal molecules301 changes depending on the strength of the horizontal electric field.Pixels oriented in this manner displays white. When there is nohorizontal electric field, the vertical electric field causes the liquidcrystal molecules 301 to return to the vertical orientation. Thus, theresponse speed of the liquid crystal molecules 301 is improved.

When a negative data signal is written, for example, a voltage of 15volts may be applied to the pixel electrode 17 and a voltage of 0 voltsmay be applied to the common electrode 18 and common electrode line 18L,in which case liquid crystal molecules 301 are oriented as shown in FIG.55B, displaying white. Under this condition, a voltage of 0 volts on thepixel electrode 17 causes the liquid crystal molecules 301 to beoriented as shown in FIG. 55A (i.e. vertically oriented), displayingblack.

In the present embodiment, as is the case in the present embodiment, thegate line 13G is driven by a gate driver 11 provided in the displayregion. Further, a COM driver for controlling the potentials of thecommon electrode 18 and common electrode line 18L is provided in thedisplay region.

As is the case in the above fourteenth embodiment, the gate driver 11and COM driver of the present embodiment are constructed such that theelements constituting the COM driver is integrated with the gate driver11. An equivalent circuit of the gate driver 11 and COM driver of thepresent embodiment is the same as that of FIG. 49. Further, the elementsconstituting the gate driver 11 and COM driver of the present embodimentare provided in the display region, as is the case with the aboveelements of FIGS. 50A and 50B, and a timing chart for illustrating thedriving of the pixel is the same as the above chart of FIG. 52.

Thus, when, as shown in FIG. 52, in the mth frame the potential of theline CL(n) goes to H level and the potentials of the common electrodeline 18L: COM(n) and common electrode 18 transition to H level, thepotential of the pixel PIX(n) is positively amplified. Then, the gateline 13G: GL(n) is driven, and a negative data signal is supplied to thesource line 15S. Thus, the potential of the pixel PIX(n) is negativelyamplified depending on the data signal and the potentials of the commonelectrode line 18L: COM(n) and common electrode 18, and is maintaineduntil the m+lth frame.

In the m+1th frame, the potentials of the common electrode line 18L:COM(n) and common electrode 18 transition from H level to L level, andthe potential of the pixel PIX(n) is negatively amplified. Then, thegate line 13G: GL(n) is driven and a positive data signal is supplied tothe source line 15S. Thus, the potential of the pixel PIX(n) ispositively amplified depending on the data signal and the potentials ofthe common electrode line 18L: COM(n) and common electrode 18, and ismaintained until the m+2th frame.

Thus, using both a vertical electrode field and a horizontal electrodefield increases the response speed of the liquid crystal layer 30 ineach pixel. Further, providing in the display region the COM driver forcontrolling the potentials of the common electrode line 18L and commonelectrode 18 and the gate driver 11 for driving the gate line 13Greduces the width of the portions of the picture frame that are alongthe sides of the display device other than that one having the sourcedriver 3.

Although embodiments of the present invention have been described, theabove embodiments are merely examples that may be used to carry out thepresent invention. Thus, the present invention is not limited to theabove embodiments, and can be carried out with appropriate modificationsto or combinations of the above embodiments without departing from thespirit of the present invention. Variations of the present inventionwill be described below.

<Variations>

(1) The above first to fifteenth embodiments describe implementationswhere the TFT-F (see FIGS. 8C and 10B) is located in one pixel region;alternatively, the TFT-F may be located in a plurality of pixel regions.FIG. 56 is a plan view of an example of how the TFT-F may be connectedaccording to the present variation. As shown in FIG. 56, The TFT-F isconstructed such that a TFT-F1 and a TFT-F2, provided in two pixelregions P31 and P32, are connected in parallel. In each of the pixelregions P31 and P 32 are provided a line 15L1 and a drain terminal 15 dfor the TFT-F1 or TFT-F2 formed by the source line layer 15. Further, aline 13N formed by the gate line layer 13 is located in the pixelregions P31 and P32, while a gate terminal 13 g is provided for each ofthe TFT-F1 and TFT-F2 connected with the lines 13N. The source terminals15s of the TFT-F1 and TFT-F2 are connected with the gate line 13G: GL(n)via the contact CH5.

A clock signal (CKA) is supplied to the TFT-F1 and TFT-F2 via the lines15L1, and the potential of the netA is provided to the gate line 13Gfrom the TFT-F1 and TFT-F2 via the contact CH5. Thus, as the TFT-F andTFT-D, which have a larger output than the other TFTs, are each locatedin a plurality of pixel regions, the decrease in the aperture ratio ofthe pixel region is reduced and each TFT itself is constructed with alarger size.

(2) The above first embodiment describes an implementation where theswitching elements of a gate driver 11 and line 15L1 are provided in thepixel regions of all colors; alternatively, starting from one of thefirst to fifteenth embodiments, the elements constituting parts of thedriving circuits such as gate drivers 11 and CS drivers 80 may beprovided in the pixel regions of a specified color. FIG. 57 is a planview of an example of how the switching elements (for example, TFT-A)constituting a part of a gate driver 11 may be connected according tothe present variation. As shown in FIG. 57, lines 15L1 for supplying apower supply voltage signal (VSS) and reset signal (CLR) to the TFT-Aare provided in blue (B) pixel regions P41B and P42B. Further, the TFT-Ais provided in the pixel region P41B. The gate terminal 13 g of theTFT-A is located in the pixel regions P41B to P42B so as to be connectedwith the line 15L1 via the contact CH2 of the pixel region P42B. Thus,as TFTs and lines 15L1 are provided in the pixels of a specified color,the elements constituting parts of the gate driver 11 are furtherdispersed, thereby minimizing the decrease in the aperture ratio.Further, as switching elements and lines are provided in blue (B)pixels, which affect luminance to a less degree than red (R) and green(G) pixels, the decrease in luminance due to the presence of a gatedriver 11 in a pixel region is reduced.

(3) Starting from the above Variation (2), pixel regions having elementsconstituting parts of a driving circuit may be larger than pixel regionsfor other colors. FIG. 58 is a plan view showing pixel regions in whichelements (for example, TFT-A and line 15L1) constituting parts of a gatedriver 11 are provided. As shown in FIG. 58, the pixel regions P41B andP42B, in which the TFT-A and line 15L1 are provided, have a horizontaldimension (i.e. that in the direction in which the source lines 15S arearranged) that is larger than that of pixel regions of other colors.Thus, the red (R), green (G) and blue (B) pixel regions have a generallyuniform aperture ratio compared with that of Variation (2), therebyreducing the variation in color balance caused by differences inaperture ratio.

(4) The above first embodiment describes implementations where a shieldlayer 16 is provided between the pixel electrode 17 and gate driver 11to prevent interference between the gate driver 11 and pixel electrode17 provided in a pixel region. Starting from one of the second tofifteenth embodiments, such a shield layer 16 may be provided betweenthe elements constituting the driving circuit and the pixel electrode.Further, starting from one of the first to fifteenth embodiments, noshield layer 16 may be provided and the elements of the driving circuitmay be arranged in pixel regions so as not to overlie the pixelelectrodes. FIG. 59 is a plan view of pixel regions where the TFT-A isprovided as an element constituting a part of the gate driver 11. Asshown in FIG. 59, the TFT-A and line 13N and lines 15L1 are located soas not to overlie the pixel region 17. This reduces the parasiticcapacitance produced between a switching element and line constitutingparts of the gate driver 11, and the pixel electrode 17, therebyachieving appropriate image display.

(5) Starting from one of the above first to fifteenth embodiments, theline 13N and line 15L1 (i.e. lines) constituting parts of the gatedriver 11 may be provided in locations in the pixel regions that dependon the display mode of the liquid crystal. Examples of linesarrangements for various display modes, i.e. VA mode, FFS mode andin-plane switching (IPS) mode will be described below.

FIG. 60A is a plan view of an example of how lines may be arranged forthe VA mode. This drawing illustrates a region in which the elementsconstituting the TFT-A are provided. As shown in FIG. 60A, theorientation film provided on each of the active-matrix substrate 20 aand counter-substrate 20 b is divided into four areas of differentorientations such that, when the orientation film is illuminated from aplurality of directions, liquid crystal molecules in one pixel regionare oriented in four directions, indicated by arrows 50 a, 50 b, 50 cand 50 d. At the boundaries between the areas of different orientations,liquid crystal molecules hit each other, which results in areas whereliquid crystal molecules are oriented in a direction extending along thepolarizing axis of the linear polarizer. Light transmission is low inthese areas, producing dark lines.

In FIG. 60A, the broken lines 51 indicate areas where dark lines appear(hereinafter referred to as dark-line region). When there are dark-lineregions 51, as in FIG. 60A, the lines 15L1 and line 13N may be providedso as to overlie the dark-line regions 51. This reduces the decrease inlight transmission in the pixel regions where the gate driver 11 ispresent.

Further, if a TFT, such as a TFT-A or TFT-D, is located in a pluralityof pixel regions, for example, a line 15L3 that has substantially thesame size as the drain terminal 15 sd 1 of the element A1 of the TFT-Alocated in the pixel region to the left in FIG. 60A may be connectedwith the line 13N of the pixel region to the right via a contact CH2.Thus, the pixel regions have a generally uniform aperture ratio.

An arrangement for the FFS mode will be described below. FIG. 60B is aplan view of an example of how lines may be arranged for the FFS mode.In FIG. 60B, the pixel electrode 17 of each pixel region has a pluralityof slits 171 (171 a and 171 b). In FIG. 60B, slits 171 a are provided inthe upper portion of the pixel electrode 17, while slits 171 b areprovided in the lower portion. For each pixel region, the slits 171 aand the slits 171 b form an angle that results in these groups of slitsbeing generally mirror images of each other with respect to the boundarybetween the group of slits 171 a and the group of slits 171 b. Thus, theorientation film is divided into areas with two different orientationdirections of liquid crystal molecules. In the implementation of FIG.60B, the portions indicated by broken line 52 that forms the boundarybetween two areas with different orientation directions form dark-lineregions. In this case, the line 13N may be provided to overlie thedark-line region 52. Further, as is the case in the arrangement of FIG.60A, a line 15L3 that has substantially the same size as the drainterminal 15 sd 1 of the element A1 of the TFT-A may be connected withthe line 13N in the pixel region to the right.

An arrangement for the IPS mode will be described below. FIG. 60C is aplan view of an example of how lines may be arranged for the IPS mode.As shown in FIG. 60C, a comb teeth-shaped pixel electrode 17 is providedin each pixel electrode. On the active-matrix substrate 20 a is furtherprovided a common electrode 18 located to overlie a part of thelight-shielding region BM, source lines 15S and lines 15L1. In theregion other than the light-shielding region BM, the source lines 15S,lines 15L1, pixel electrodes 17 and common electrode 18 are bent to haveportions in two different directions connected generally at the centerof their extension. The comb-teeth-shaped pixel electrode 17 and commonelectrode 18 produce a horizontal electric field such that liquidcrystal molecules in each pixel region are controlled to be oriented intwo directions. As shown in FIG. 60C, in this case, switching elementsconstituting parts of the gate driver 11 and line 13N and lines 15L1 maybe provided in the lower portion of the common electrode 18. Thisconstruction reduces the parasitic capacitance produced between thepixel electrode 17 and gate driver 11.

(6) A plurality of display panels 2 according to one of the above firstto fifteenth embodiments may be arranged to form a large display. Asshown in FIG. 61A, as is the case in the first embodiment, the pictureframe region 2Ra includes terminals 12 g (not shown). The other pictureframe regions 2Rb, 2Rc and 2Rd have a smaller width than the pictureframe region 2Ra. As shown in FIG. 61B, a plurality of display panels 2may be arranged such that the picture frame region 2Ra of each panel ison the periphery to form a tiled large panel 2B. In this case, the threesides of a display panel 2, i.e. the picture frame regions 2Rb, 2Rc and2Rd have a smaller width such that the boundaries inside the displaypanel 2 cannot easily be seen.

(7) Starting from one of the above first to fifteenth arrangements, thegate driver 11 may be constructed in the following manner. FIG. 62 showsan example equivalent circuit of a gate driver according to the presentvariation. As shown in FIG. 62, in addition to the components shown inFIG. 4, the gate driver 11 a includes a capacitor Cab connected betweenthe netA and netB.

As discussed above, the elements constituting the gate driver 11 areprovided in pixel regions. As such, a parasitic capacitance may beproduced between the line 13N for the netA and netB formed by the gateline layer 13 and the source line 15S, potentially causing noise at gatelines 13G. For example, in the pixel region where the TFT-A is providedshown in FIG. 63A, a parasitic capacitance may be produced between thesource line Sla(15S) and SLb(15S) and the line 13N for the netA. FIG.63B is a waveform diagram showing signals encountered when such aparasitic capacitance is produced.

As shown in FIG. 63B, during time t1 to t2 in which the clock signal(CKB) is at L level and the clock signal (CKA) is at H level, when thesource line Sla and LSb display an image that requires the potentials ofthese lines to be relatively high, a parasitic capacitance occursbetween the line 13N for the netA and the source lines SLa and SLb suchthat the TFT-F cannot remain off, producing noise at the gate line 13G:GL(n). During time t1 to t2, the TFT-C for maintaining the netA at Llevel is off such that the gate line 13G: GL(n) is susceptible to theinfluence from the source lines SLa and SLb during this period. On theother hand, during time t4 to t5 in which the clock signal (CKB) is at Hlevel, the TFT-C and TFT-D are on. Thus, the potential of the line 13Nfor the netA and the gate line 13G: GL(n) is maintained at L level andis thus not affected by variations in the potentials of the source linesSLa and SLb.

If noise occurs during a period where the potential of the gate line 13Gis L level, the off margin of the TFT-PIX may decrease, potentiallycausing a malfunction. Particularly, noise often occurs when thepolarity pattern is as described below. FIGS. 64A to 64C each show apattern of polarities of pixel regions that often cause noise. Theregion P indicated by a rectangle in FIGS. 64A to 64C is a pixel region.The character “+” or “−” in the region P indicates the polarity of thepixel region. FIG. 64A shows a polarity pattern encountered when whiteis displayed by line inversion driving in normally black mode. FIG. 64Bshows a polarity pattern encountered when white and black lines aredisplayed by dot inversion driving in normally black mode. FIG. 64Cshows a polarity pattern encountered when a white and black zigzagpattern is displayed by source inversion driving in normally black mode.

In the present variation, as shown in FIG. 62, a capacitor Cab isprovided between the netA and netB to reduce noise in the waveform ofnetA shown in FIG. 63B such that the TFT-F remains off. FIG. 65 showswaveforms encountered when a capacitor Cab is provided if the polaritypattern is as shown in FIG. 64A or 64C. If no capacitor Cab is provided,as shown in FIG. 63B, during time t1 to t2, a parasitic capacitanceoccurs between the netA and source lines SLa and SLb such that thepotential of the netA cannot remain at L level. If the capacitor Cab isprovided, at time t1, the potential of the netA is upthrusted and, atthe same time, a variation in the potential of the netB draws thepotential of netA down to L level. As a result, as shown in FIG. 65, thepotential of the netA remains at L level in time t1 to t2 such that theTFT-F remains off, thereby reducing noise at the gate line 13G: GL(n).

The capacitor Cab may also be connected in the following manner. FIG. 66is a schematic view of pixel regions where a capacitor Cab and TFT-C areprovided. As shown in FIG. 66, in the pixel region P51, the TFT-PIX isconnected with the pixel electrode 17 via a contact CH1. Further, thegate line layer 13 forms one electrode 13 c 1 of the capacitor Cab andthe gate line 13G and line 13Na. The source line layer 15 forms theother electrode 15 c 1 of the capacitor Cab and the source line 15S andline 15L1. The electrode 15 c 1 is connected with the line 13Na for thenetA via the contact CH2. The electrode 13 c 1 of the capacitor Cab islocated in the pixel regions P51 and P52, and is connected with the line13Nb for the netB.

(8) The above first to fifteenth embodiments describe implementationswhere the semiconductor layer portions 14 in the switching elementsconstituting parts of the gate driver 11 are made of an oxidesemiconductor; alternatively, the semiconductor layer portions 14 may bemade of polysilicon or amorphous silicon.

(9) The above first to fifteenth embodiments describe implementationswhere on the substrate 20 of the active-matrix substrate 20 a areprovided gate lines 13G, source lines 15S, gate drivers 11, terminals 12g for receiving control signals and the like for the gate drivers 11,and terminals 12 s for receiving data signals and the like for thesource lines 15S; in addition, a source driver 3 and display controlcircuit 4 may be provided.

(10) The above first to fifteenth embodiments describe implementationswhere the display panel 2 is a liquid crystal panel; alternatively, itmay be a panel using organic electroluminescence (EL). An implementationwith an organic EL panel will be described below.

FIG. 67 shows an equivalent circuit of a pixel of a display panel 2′according to the present variation. As shown in FIG. 67, in the pixelPIX′(n) are provided switching elements T1 to T1 made of thin-filmtransistors, capacitors C1 and C2 and an organic light-emitting device(OLED) 90. In the pixel PIX′(n) are further provided a light-emissioncontrol line 91 extending generally parallel to the gate line 13G, and apower supply line 92 (EL(n−1)) extending generally parallel to the dataline 15S.

The gate terminals of the elements T3 and T4 are connected with the gateline 13G of the preceding row (GL(n−1)). The element T3 has a sourceterminal connected wih the power supply line 92, and a drain terminalconnected with one electrode (hereinafter referred to as firstelectrode) of each of the capacitors C1 and C2 and the drain terminal ofthe element T1.

As the gate line 13G: GL(N−1) is driven, the element T3 turns on suchthat the voltage signal EVDD supplied to the power supply line 92 issupplied to the capacitors C1 and C2.

The element T4 has a drain terminal connected with the other electrode(hereinafter referred to as second electrode) of the capacitor C1 andthe gate terminal of the TFT-T2, and a source terminal connected withthe drain terminal of the element T2. As the gate line 13G: GL(n−1) isdriven, the element T4 turns on, which, together with the element T2,constitutes a diode connection.

The element T1 is connected with the gate line 13G: GL(n) and the dataline 15S. When the gate line 13G: GL(n) is selected, the element T1turns on, and the data signal Vdata supplied to the data line 15S issupplied to the first electrode of the capacitor C1.

The element T2 has a source terminal connected with the second electrodeof the capacitor C2 and the power supply line 92, and a drain terminalconnected with the OLED 90 via the element T5.

The element T5 (i.e. switching element for controlling light emission)is connected between the drain terminal of the element T2 and the anodeof the OLED 90. The gate terminal of the element T5 is connected withthe light-emission control line 91 of the preceding row (EL(n−1)).Depending on the potential of the light-emission control line 91:EL(n−1), the element T5 disconnect the OLED 90 from the element T2. TheOLED 90 emits light depending on the current from the element T2 via theelement T5.

In the present variation, the potential of the light-emission controlline 91 is controlled by an EL driver (i.e. light control line driver)provided in the display region. FIG. 68A shows an equivalent circuit ofan EL driver for controlling the potential of the light-emission controlline 91: EL(n−1). As shown in FIG. 68A, the EL driver 93 includesswitching elements L and M each made of a thin-film transistor.

The switching element L includes switching sub-elements L1 and L2connected in series. The gate terminals of the switching sub-elements L1and L2 are connected with the drain terminal of the switchingsub-element L1. The power supply voltage signal VDD is supplied to thedrain terminal of the sub-element L1. Thus, the power supply voltagesignal VDD is constantly supplied to the light-emission control line 91:EL(n−1) via the switching element L. The switching element L may be, forexample, a dual-gate switching element or a switching element with alarger channel length than the switching element M so as to have asmaller driving capability than the switching element M.

The switching element M has a gate terminal connected with the gate line13G: GL(n−1) and a drain terminal connected with the light emissioncontrol line 91: EL(n−1). The power supply voltage signal VSS issupplied to the source terminal of the switching element M. When thegate line 13G: GL(n−1) is driven, the switching element M turns on, andthe power supply voltage signal VSS is supplied thereto.

As discussed above, the power supply voltage signal VDD is constantlysupplied to the light-emission control line 91: EL(n−1) via theswitching element L, and the switching element L is constructed suchthat the switching element M has a higher driving capability. Thus, asshown in FIG. 68B, during time tO to tl where the potential of the gateline 13G: GL(n−1) goes to H level, the light-emission control line 91:EL(n−1) is charged to the power supply voltage signal VSS. On the otherhand, after time t1 at which the potential of the gate line 13G: GL(n−1)goes to L level and the potential of the gate line 13G: GL(n) goes to Hlevel, the light-emission control line 91: EL(n−1) is charged to thepower supply voltage signal VDD.

An example arrangement of the elements constituting the gate driver 11and EL driver 93 of the present variation in display regions will bedescribed below. FIGS. 69A to 69E are schematic plan views of pixelregions in which the elements of gate drivers 11 and EL drivers 93 areprovided. The pixel regions of FIGS. 69A to 69E form a single continuousarea.

As shown in FIGS. 69A to 69E, in the present variation, in each pixelare provided a gate line 13G for the row having this pixel and a gateline 13G for acquiring the output of the gate line 13G for the pixels ofthe preceding row (hereinafter referred to as preceding gate line) so asto extend generally parallel to each other.

For example, in the pixel PIX′(n) shown in FIG. 69A, the preceding gateline 13G: GL(n−1) and the gate line 13G: GL(n) are provided. Dependingon the output of the preceding gate line 13G: GL(n−1), the gate line13G: GL(n) is driven and data is written to the pixel PIX′(n). Further,in the pixel PIX′(n−1) in the row preceding the row having the pixelPIX′(n) are provided the gate line 13G: GL(n−1) and the preceding gateline 13G: GL(n−2). Depending on the output of the preceding gate line13G: GL(n−2), the gate line 13G:GL(n−1) is driven and data is written tothe pixel PIX′(n−1). The preceding gate line 13G is connected with theassociated gate line 13G via the line 95 shown in FIG. 69E. For example,when the gate line 13G: GL(n) is driven by a gate driver 11, the outputis supplied to the pixels of the row GL(n+1) via the preceding gate line13G: GL(n) which are in the pixels of the row GL(n+1).

Although FIGS. 69A and 69B do not have the character “TFT”, “A” to “J”,“L”, and “M” indicate TFT-A to TFT-J, TFT-L and TFT-M. As is the case inthe above first embodiment, the elements constituting the gate driver 11for driving a gate line 13G (TFT-A to J, Cbst) are dispersed in pixelregions. Further, in the pixel regions of the columns in which thoseelements of gate drivers 11 that receive control signals (CKA, CKB, VSSand CLR) are provided, lines 15L1 are provided for supplying the controlsignals.

The switching elements L and M of an EL driver 93 are provided for eachlight-emission control line EL(91). The switching element M is locatedin pixel regions of the columns 301 x to 302 x. The switching element Lis located in pixel regions of the columns 303 x to 304 x. Lines 15L1for supplying the power supply voltage signals VSS and VDD are providedin the columns 302 x and 304 x, in which the switching elements M and Lare provided. Thus, the elements constituting an EL driver 93 areprovided in pixel regions in which the elements of a gate driver 11 arenot present.

FIG. 70 shows a timing chart showing the timing for driving the pixelPIX′ shown in FIG. 67. In FIG. 70, during time period t1, the potentialof the light-emission control line 91: EL(n−1) is at L level, and thepotential of the gate line 13G: GL(n−1) is at H level. In this state,the element T5 is off and the OLED 90 is disconnected from the elementT2. Further, since the element T3 is on, the portion V1 of FIG. 67 ischarged to the voltage signal EVDD which is supplied from the powersupply line 92. Further, since the element T4 is on, the portions V2 andV3 of FIG. 67 are short-circuited, and are charged to the thresholdvoltage Vth of the voltage signal EVDD+T2.

After time period t1, in time period t2, the potential of thelight-emission control line 91: EL(n−1) goes to H level, the potentialof the gate line 13G: GL(n−1) goes to L level, and the potential of thegate line 13G: GL(n) goes to H level. The data signal Vdata is suppliedto the source line 15S at the time point at which the gate line 13G:GL(n) goes to H level. In this state, the element T5 is on such that theOLED 90 is connected with the element T2. Further, the element T3 is offand the element T1 is on such that the portion V1 of FIG. 67 is chargedto the data signal Vdata.

Further, since the element T4 is off, the portion V2 of FIG. 67 isaffected by the variation in the potential of the portion V1 via thecapacitor C1. Thus, the voltage of the portion V2 changes to: voltagesignal EVDD+threshold voltage Vth+A×(data signal Vdata−voltage signalEVDD). Here, A=C1/(C1+Cp) (C1: capacitance of the capacitor C1; Cp:parasitic capacitance or the like of the switching element). At thismoment, the potential of the portion V3 in FIG. 67 becomes the valuethat is lower by the threshold voltage Vth of the element T2. That is,V3=voltage signal EVDD+A×(data signal Vdata−voltage signal EVDD). Thus,a current that is independent from the threshold voltage Vth flows intothe portion V3, thereby eliminating variations in the threshold voltageVth.

(11) The above fifth embodiment describes an implementation where twogate lines 13G are driven simultaneously by one pair of gate drivers(11_a and 11_b); alternatively, they may be driven by two or more pairsof gate drivers. For example, as shown in FIG. 71, in addition to onepair of gate driver groups (11_a and 11_b) described above, a gatedriver group 11_c (gate drivers 11(c 1) to 11(c 7)) and a gate drivergroup 11_d (gate drivers 11(d 1) to 11(d 7)) that are similar to thegate driver groups (11_a and 11_b) may be provided. The gate drivergroups 11_c and 11_d are provided in columns other than those for thegate drive groups 11_a and 11_b. In this case, the start pulse signal Sais supplied to the gate driver group 11_c at the same time point as thatfor the gate driver group 11_a, and the start pulse signal Sb issupplied to the gate driver group 11_d at the same time point as thatfor the gate driver group 11_b. Thus, the gate driver 11 (an) in thegate driver group 11_a and the gate driver 11 (cn) of the gate drivergroup 11_c drive the gate line 13G of the nth row (n is an integer,1≦n≦7) in a synchronized manner. Then, after the driving by the gatedriver groups 11_a and 11_c, the gate driver 11(bn) of the gate drivergroup 11_b and the gate driver 11(dn) of the gate driver group 11_ddrive the gate line 13G of the nth row in a synchronized manner.

(12) Starting from one the above first, third, sixth to eighthembodiments and the above variations (1) to (9), gate drivers 11 may bearranged in the following manner.

(12-1: Example Arrangement 1)

In the present variation, the gate drivers 11 provided for the gatelines 13G of the even-numbered rows (hereinafter referred to as gatedrivers 11 x) are connected via a line 15L1, and the gate drivers 11provided for the gate lines 13G of the odd-numbered rows (hereinafterreferred to as gate drivers 11 y) are connected via a line 15L1. Then,the gate drivers 11 x and the gate drivers 11 y are driven separately tosequentially drive all the gate lines 13G.

FIG. 72 is a schematic diagram of an active-matrix substrate 20 aaccording to the present variation. In this drawing, for convenience,the source line 15S and first terminals 12 s are not shown. Asillustrated in FIG. 72, M gate lines 13G: GL(1) to GL(M) are provided onthe active-matrix substrate 20 a. On the active-matrix substrate 20 a,the gate drivers 11 x provided for the gate lines 13G of theeven-numbered rows (GL(2), GL(4), . . . GL(M)) are located in the samecolumns and connected with each other via a line 15L1. Further, the gatedrivers 11 y provided for the gate lines 13G of the odd-numbered rows(GL(1) to GL(M−1)) are located in the same columns and connected witheach other via a line 15L1. The gate drivers 11 x are located in pixelregions of columns that are different from those for the gate drivers 11y.

Each of the gate drivers 11 x and 11 y has the same circuit constructionas the gate driver 11 of the first embodiment (see FIG. 4). FIG. 73Ashows an equivalent circuit of gate drivers 11 x provided in the displayregion, while FIG. 73B shows an equivalent circuit of gate drivers 11 yprovided in the display region. Although FIGS. 73A and 73B do not havethe character “TFT” for convenience, “A” to “J” in the drawings indicate“TFT-A” to “TFT-J” of FIG. 4.

As illustrated in FIG. 73A, a gate driver 11 x for driving the gate line13G: GL(n) (hereinafter referred to as gate driver 11 x(n)) is providedbetween the lines GL(n) and GL(n−1). A gate driver 11 x for driving thegate line 13G: GL(n+2) (hereinafter referred to as gate driver 11x(n+2)) is provided between the rows GL(n+2) and GL(n). The TFT-A toTFT-J, capacitor Cbst, internal nodes (netA(n), netA(n+2), netB(n) andnetB(n+2)) constituting the gate driver 11 x are provided in pixelregions in columns 400A and in the row in which the gate driver isprovided. In FIG. 73A, lines 15L1 extending generally parallel to thesource lines 15S are provided in the pixel regions of the columns inwhich the elements receiving the control signals (VSS, CLR, CKA and CKB)are provided and the nearby columns. The adjacent gate drivers 11 x(n)and 11 x(n+2) are connected via a line 15L1.

Further, as illustrated in FIG. 73B, a gate driver 11 y for driving thegate line 13G: GL(n−1) (hereinafter referred to as gate driver 11y(n−1)) is provided between the rows GL(n−2) and GL(n−1). A gate driver11 y for driving the gate line 13G: GL(n+1) (hereinafter referred to asgate driver 11 y(n+1)) is provided between the rows GL(n+1) and GL(n).The TFT-A to TFT-J, capacitor Cbst, internal nodes (netA(n−1),netA(n+1), netB(n−1) and netB(n+1)) constituting the gate driver 11 yare provided in pixel regions in columns 400B and in the row in whichthe gate driver is provided. In FIG. 73B, lines 15L1 extending generallyparallel to the source lines 15S are provided in the columns in whichthe elements receiving the control signals (VSS, CLR, CKA and CKB) areprovided and the nearby columns. The adjacent gate drivers 11 y(n−1) and11 y(n+1) are connected via a line 15L1.

The size of a pixel region in a row in which a gate driver 11 x or 11 yare provided will be described below. FIG. 74 is a simplified schematicview of some pixel regions of columns 400B in which a gate driver 11 yis provided. In this drawing, the character “R”, “G” or “B” for a pixelPIX indicates the color of the color filter corresponding to the pixelPIX. Further, as is the case in the first embodiment, the region BMindicated by one-dot-chain lines indicates a light-shielding regionwhere light is blocked by the black matrix. Although not shown in thisdrawing, some of the elements constituting the gate drivers 11 y arelocated between the rows GL(n+1) and GL(n) near the gate line 13G:GL(n+1) and between the rows GL(n−1) and GL(n−2) near the gate line 13G:GL(n−1).

As shown in FIG. 74, the length 12 between the gate lines 13G where agate driver 11 y is present is greater than the length 11 between thegate lines 13G where a gate driver 11 y is not present. However,regardless of whether a gate driver 11 y is present, the length 13 ofthe aperture as measured in the direction of extension of the sourcelines 15S for each pixel PIX is substantially the same for lightshielding. Thus, the aperture ratio for each pixel is generally uniform.

That is, in the columns 400A and 400B in which gate drivers 11 x and 11y are provided, the distance between the gate lines 13G where a the gatedriver 11 x or 11Y is present is larger than the distance between thegate lines 13G where a gate driver 11 x or 11 y is not present. Further,the light-shielding region of the pixel regions of a row in which a gatedriver 11 x or 11 y is present is larger than that of the pixel regionsof a row in which a gate driver 11 x or 11 y is not present such thatthe aperture ratio of every pixel region is substantially the same.

Thus, in a region where a gate driver is provided, a gate driver is notpresent in all the spaces between the gate lines, thereby improving theaperture ratio compared with implementations where a gate driver ispresent in all the spaces between the gate lines.

If gate drivers 11 x and 11 y are provided such that there is a spacebetween a region in which a gate driver 11 x is present and a region inwhich a gate driver 11 y is present, the distance between the gate lines13G in this space (hereinafter referred to as no-gate driver region) maybe substantially the same. More specifically, for example, the distancebetween gate lines 13G in a no-gate driver region may have theintermediate value between the distance 11 between gate lines 13G ofrows in which a gate driver 11 x or 11 y is not present shown in FIG. 74and the distance 12 of gate lines 13G of rows in which a gate driver 11x or 11 y is present. Further, light may be shielded for the no-gatedriver regions such that the width in the vertical direction (i.e. they-direction in FIG. 74) of an aperture of a pixel region in a no-gatedriver region is equal to the width of an aperture in a region in whicha gate driver 11 x or 11 y is present (i.e. the width 13 in FIG. 74).More specifically, for example, the width in the vertical direction(i.e. the y-direction in FIG. 74) of the portions of the light-shieldingregion BM that cover gate lines 13G of no-gate driver regions may havethe intermediate value of the width of the portions of thelight-shielding region MB that cover the gate line 13G: GL(n+1) shown inFIG. 74 and the width of the light-shielding region MB covering the gateline 13G: GL(n) shown in FIG. 74.

(12-2: Example Arrangement 2)

An example arrangement where gate drivers 11 x and 11 y are disposedonly in the pixels for one of the colors R, G and B will be describedbelow. FIG. 75A is a simplified schematic view of a portion of thedisplay region in an implementation where the TFT-A to TFT-J andcapacitor Cbst constituting a gate driver 11 y are disposed in B pixels.Although the following describes an example arrangement of gate drivers11 y, gate drivers 11 x may be disposed in a manner similar to that ofFIG. 75A.

As shown in FIG. 75A, the width lx1 of B pixels in the x-direction islarger than the width lx2 of pixels R and G in the x-direction. Further,the width of R and G pixels in the y-direction has substantially thesame length ly2 regardless of whether a gate driver 11 y is present. Onthe other hand, the width of B pixels in the y-direction variesdepending on whether the gate driver 11 is present or not. That is, theB pixels in rows in which a gate driver 11 y is present has a width ly1that is larger than the width ly2 of R and G pixels in the y-direction.Further, the B pixels in rows in which a gate driver 11 y is not presenthas a width ly3 that is smaller than the width ly2 of R and G pixels inthe y-direction. That is, as shown in FIG. 75A, one of the pair of gatelines 13G forming a row in which a gate driver 11 y is present hasportions that correspond to B pixels in this row and that are displacedoutwardly with respect to the portions corresponding to the R and Gpixels. The other one of the pair of gate lines 13G forming the row inwhich a gate driver 11 y is present are substantially in a straight linewith respect to all the portions corresponding to the R, G and B pixelsin this row.

Further, as shown in FIG. 75A, light is blocked for the portion in whichan element of a gate driver 11 y is provided such that the B pixels inthe row in which the gate driver 11 y is present have substantially thesame aperture ratio. FIG. 75B shows an enlarged schematic view of theportion defined by the broken circle 401 shown in FIG. 75A.

As shown in FIG. 75B, the portions of the gate 13G corresponding to Band R pixels are generally perpendicular to the source line 15S (see13G(B) and 13G(R)), and the portion thereof that crosses the source line15S is diagonal to the source line 15S (i.e. non-perpendicular). Theportions of the light-shielding region that correspond to a B pixel hasa range of ±Δd2 in the y-direction with respect to the one-dot-chainline ◯ which passes near the central axis of the portions of the gateline 13G(R) that correspond to the R pixel, and has a width in they-direction of d2(=2·Δd2). The portions of the light-shielding regionthat correspond to the R pixel has a range of ±Δd1 in the y-directionwith respect to the one-dot-chain line ◯, and has a width in they-direction of d1(=2·Δd1).

(12-3: Example Arrangement 3)

The higher the resolution of the display panel, the more difficult it isto dispose the elements constituting gate drivers in pixels. In view ofthis, the distance between the source lines 15S forming a pixel in whichan element of a gate driver is provided may be larger in its portionwith the element than in the other portions.

FIG. 76A shows an implementation where the distance between the sourcelines 15S forming a B pixel in which an element of a gate driver 11 y asshown in FIG. 75A is provided, in its portion with the element of thesource driver 11 y, i.e. in the portion with the light-shielding region,is larger than the aperture of the B pixel. FIG. 76B is an enlargedschematic view of the portion defined by the broken ellipse 402 shown inFIG. 76A. As shown in FIG. 76B, one of the source lines 15S forming a Bpixel, in the portion with the width d2 of the light-shielding region BMof the B pixel in the y-direction, is located outward, or displacedtoward the adjacent R pixel, by Δd. The arrangement shown in FIGS. 76Aand 76B provides a larger region in which an element of a gate driver 11y is provided than an implementation of FIG. 75A, thereby making iteasier to dispose elements of gate drivers 11 y in B pixels.

(12-4: Example Arrangement 4)

FIGS. 73A and 73B illustrate implementations where the elements andinternal node lines constituting gate drivers 11 x and 11 y are disposedin one row between gate lines 13G; alternatively, the elements andinternal node lines constituting gate drivers 11 x and 11 y may bedisposed in pixel regions of a plurality of rows. A specificimplementation of such an arrangement is shown in FIG. 77.

FIG. 77 shows an example arrangement of elements and internal node linesconstituting the gate driver 11 x(n) for driving the gate line 13G:GL(n). Although FIG. 77 does not have the character “TFT-”, “A” to “J”in FIG. 77 indicate TFT-A to TFT-J. As shown in FIG. 77, the TFT-A toTFT-J and capacitor Cbst constituting a gate driver 11 x(n) is disposedbetween the gate lines 13G: GL(n) and GL(n−1). The netA(n) and netB(n),which are internal nodes for the gate driver 11x(n), are disposedbetween the gate lines 13G: G(n+1) and GL(n). Internal node lines N1 toN3 are disposed between the gate lines 13G: GL(N−1) and GL(n−2).

The internal node line N1 connects the source terminals of the TFT-H, Iand J, and is connected with a line 15L1 to which the power supplyvoltage VSS is supplied. The internal node line N2 is connected with thedrain terminal of the TFT-G and a line 15L1 to which the clock signalCKB is supplied. The internal node line N3 connects the source terminalsof the TFT-A, C and D and is connected with a line 15L1 to which thepower supply voltage VSS is supplied.

In this arrangement, the pixel region 403 in which the TFT-H is providedshown in FIG. 77, for example, only needs to have a line for connectingto the line 15L1 supplying the clock signal CKA, a line for connectingthe drain terminal of the TFT-H with the netB(n) and a line forconnecting the source terminal of the TFT-H with the internal node lineN1. In the implementation of FIG. 73A, the netB(n) is provided in thepixel region having the TFT-H, while in the implementation of FIG. 77,the netB(n) is provided in pixel regions of the preceding row, reducingthe number of lines in the TFT-H, thereby improving the aperture ratio.

(12-5: Example Arrangement 5)

In one of the above implementations, in the display region of theactive-matrix substrate 20 a, the regions made of two different columns400A and 400B include gate drivers 11 x for driving the gate lines 13Gof even-numbered rows and gate drivers 11 y for driving the gate lines13G of odd-numbered rows; alternatively, for example, the display regionmay include, in three regions extending in the extension direction ofthe gate lines 13, gate drivers for driving the gate line 13G of the3n−2th row, gate drivers for driving the gate line 13G of the 3n−1throw, and gate drivers for driving the gate line 13G of the 3nth row. Thepresent variation only requires that, in the display region, a gatedriver 11 be provided in each of K regions (K is an integer, K≧2)arranged in a direction in which the gate lines 13G extend, each gatedriver being provided for every K gate lines, gate drivers beingprovided on different gate lines 13G in different regions.

(13) In the above fourteenth embodiment, an electric short circuitbetween a pixel electrode 17 and the common electrode 18 may cause aproblem called bright spot at a pixel. If the pixel with a bright spotis a pixel in which dummy lines 15L4 and 13N′ (see FIG. 25A) areprovided, a laser beam or the like may be directed to the dummy lines15L4 and 13N′ to cause a short circuit to electrically connect the pixelelectrode 17 with the common electrode 18. As no voltage is applied tothe pixel electrode 17 of the pixel with a bright spot, the commonelectrode 18 and pixel electrode 17 are at the same voltage, and thispixel region displays black (i.e. black spot). As the pixel with abright spot now has a black spot, the decrease in display quality isreduced compared with cases with a bright spot.

The present variation describes an implementation where, when a brightspot is produced at a pixel with dummy lines, the dummy lines may beshort-circuited to electrically connect the pixel electrode 17 with thecommon electrode 18; alternatively, if pixels have auxiliary capacitanceelectrodes, dummy lines may be short-circuited to connect a pixelelectrode 17 with an auxiliary capacitance electrode.

(14) The above first to fifteenth embodiments and the above variationsdescribe implementations where a line 15L1 for supplying control signalssuch as clock signals to the gate driver 11 is located near the centerof the pixel region (see FIGS. 8B to 8D); if the pixel pitch is small,as in a high-resolution display panel, a line 15L1 needs to be providedto avoid the TFT-PIX. For example, if a line 15L1 is located near onesource line 15S(b) of the pixel PIX(a) as shown in FIG. 78A, acapacitance between the line 15L1 and source line 15S(b) may cause noisein a data signal supplied to the source line 15S(b), producing luminanceunevenness. In view of this, the present variation constructs the pixelPIX(a) such that a portion of the line 15L1 is spaced apart from thesource lines 15S(a) and 15S(b) by substantially the same distance.

FIG. 78B is a schematic diagram of an example arrangement of a line 15L1according to the present variation. In the implementation of FIG. 78B,in the pixel PIX(a), the distance between the source line 15S(a) forsupplying a data signal to the pixel PIX(a) and the source line 15S(b)for supplying a data signal to the pixel PIX(b) is X. The line 15L1 hasbent portions 151 that are bent generally at a right angle within thepixel PIX(a) such that a portion of the line 15L1 is disposed to bespaced apart from the source line 15S(a) and source line 15S(b) by adistance of about X/2. This arrangement reduces the capacitance betweenthe line 15L1 and the source lines 15S(a) and 15S(b). The effects ofthis arrangement will be described below, also with reference to FIG.78A for comparison.

The distance between the line 15L1 and source line 15S(a) will berepresented by d1, the distance between the line 15L1 and source line15S(b) will be represented by d2, and the line 15L1, source line 15S(a)and 15S(b) will be considered to approximate a parallel plate capacitor.Then, the capacitance CCON-SL between the line 15L1 and the source lines15S(a) and 15S(b) for a unit length will be exuressed by the followingequation:

$\begin{matrix}{C_{{CON}\text{-}{SL}} = {{k\left( {\frac{1}{d_{1}} + \frac{1}{d_{2}}} \right)} = \frac{kx}{d_{1}d_{2}}}} & \left\lbrack {{Equation}\mspace{14mu} 1} \right\rbrack\end{matrix}$

k: constant of proportionality)

Thus, the C_(CON-SL) in the implementation of FIG. 78A is represented byC_(CON-SL) _(_)A=(36k/5)/X. The C_(CON-SL) in the implementation of FIG.78B is represented by C_(CON-SL) _(_)B=4k/X. That is, C_(CON-SL)_(_)B<C_(CON-SL) _(_)A, which means that the arrangement of the line15L1 shown in FIG. 78B has a smaller capacitance C_(CON-SL) than thearrangement of the line 15L1 shown in FIG. 78A. This reduces noise in adata signal for an adjacent pixel PIX(b), thereby reducing luminanceunevenness.

In the implementation of FIG. 78B, each of the bent portions 151 of theline 15L1 is bent generally at a right angle; alternatively, as shown inFIG. 78C, it may be bent diagonally (i.e. non-perpendicularly). Thisarrangement reduces the entire length of the line 15L1 in the pixelPIX(a) compared with the implementation of FIG. 78B, thereby reducingthe load on the line 15L1 when receiving a control signal.

FIGS. 78B and 78C show implementations where the TFT-PIX in each ofadjacent upper and lower pixels is connected with the same source line15S(a) or 15S(b); alternatively, as shown in FIGS. 79A and 79B, theTFTs-PIX of adjacent upper and lower pixels may be connected withopposite source lines 15S(a) and 15S(b). This implementation onlyrequires that the bent portions 151 of the line 15L1 be bent in thedirections opposite those of FIG. 78B and 78C.

(15) Starting from the above first to eighth embodiments and Variation(1) to (9) and (11) to (14), an auxiliary capacitance electrodeconnected with a pixel electrode may be provided. In such anarrangement, for example, as shown in FIG. 80, auxiliary capacitanceelectrodes CS connected with the pixel electrodes may be provided in thedisplay region 200, an auxiliary capacitance electrode Cs may beconnected with an auxiliary capacitance line CsL disposed along theperiphery of the auxiliary capacitance electrode Cs outside the displayregion 200, and a predetermined voltage may be applied to the auxiliarycapacitance electrodes Cs via the auxiliary capacitance line CsL. Inthis case, an auxiliary capacitance electrode Cs of a pixel in which aline 15L1 is provided may receive noise from the line 15L1. Since apixel in which no line 15L1 is provided does not receive noise from aline 15L1, the potential of a pixel electrode 17 varies depending onwhether a line 15L1 is provided in the pixel, potentially causingluminance unevenness. In the present variation, the connection portionsbetween the auxiliary capacitance electrodes Cs and auxiliarycapacitance line CsL are not only disposed along the periphery but alsowithin the display region such that the auxiliary capacitance electrodesCs are kept at a predetermined voltage. A specific description will begiven below.

(15-1: Example Arrangement 1)

FIG. 81A is a schematic diagram of a pixel in which a dummy line(adjustment line) is provided. In the implementation of this drawing, inthe pixel PIX are provided a dummy line 13N′ extending generallyparallel to the gate line 13G, a dummy line 15L4 extending generallyparallel to the source line 15S, and a low-impedance line 40 overlyingthe dummy line 15L4. In this drawing, the auxiliary capacitanceelectrode Cs is not shown. The low-impedance line 40 extends generallyparallel to the source line 15S, and the ends of the low-impedance line40 are electrically connected with auxiliary capacitance line CsLdisposed along the periphery of the area of the auxiliary capacitanceelectrodes Cs shown in FIG. 80. The low-impedance line 40 is at the samepotential as the common electrode provided on the counter-substrate 20b, and this potential may not be fixed.

FIG. 81B is a cross-sectional view of the pixel PIX of FIG. 81A takenalong line A-A. As shown in FIG. 81B, the dummy line 15L4 is located inthe source line layer 15, i.e. in the same layer as the source line 15S.A protection film 23 is provided on top of the source line layer 15. Ontop of the protection film 23 is provided a low-impedance line 40overlying the dummy line 15L4, and an auxiliary capacitance electrode Csis provided to be in contact with the low-impedance line 40. A pixelelectrode 17 is provided above the auxiliary capacitance electrode Cs,with an interlayer insulating film 24 being present in between.

Since the low-impedance line 40 is located above the dummy line 15L4 tooverlie it, the decrease in the aperture ratio of the pixel PIX due tothe presence of the low-impedance line 40 is reduced. Further, in thisimplementation, no low-impedance line 40 is provided in a pixel in whicha switching element of a gate driver 11 is provided, thereby reducingsuch a line's influence on the operation of the gate driver 11.

Further, as the low-impedance line 40 is provided, contacts between theauxiliary capacitance line CsL and auxiliary capacitance electrodes Csare provided not only along the periphery of the area of auxiliarycapacitance electrodes Cs, but also in pixels in which dummy lines 15L4are provided. Thus, even when an auxiliary capacitance electrode Cs neara low-impedance line 40 is affected by noise from a line 15L1 and itspotential is displaced from a predetermined level, a charge is suppliedthereto from the auxiliary capacitance line CsL via the low-impedanceline 40 such that the potential of the electrode returns to thepredetermined level.

(15-2: Example Arrangement 2)

In the above implementations of FIGS. 81A and 81B, the low-impedanceline 40 is provided above the dummy line 15L4; alternatively, alow-impedance line 40 that also serves as a dummy line may be providedin the source line layer 15. FIG. 82A is a schematic diagram of a pixelin such an arrangement. In the implementation of this drawing, in thepixel PIX are provided a dummy line 13N′ and a low-impedance line 40that also serves as a dummy line 15L4. The low-impedance line 40 extendsgenerally parallel to the source line 15S, and the ends of thelow-impedance line 40 are electrically connected with the auxiliarycapacitance line CsL along the periphery of the area of the auxiliarycapacitance electrode Cs shown in FIG. 80.

FIG. 82B is a cross-sectional view of the pixel PIX of FIG. 82A takenalong line B-B. As shown in FIG. 82B, in the source line layer 15 isprovided a low-impedance line 40 located between the source lines 15S.On top of the source line layer 15 is provided a protection film 23 inwhich a contact hole CH extending therethrough to the surface of thelow-impedance line 40 is formed, and an auxiliary capacitance electrodeCs is provided on top of the protection film 23. The low-impedance line40 is connected with the auxiliary capacitance electrode Cs via thecontact hole CH.

Since the low-impedance line 40 is connected with the auxiliarycapacitance electrode Cs and auxiliary capacitance line CsL, theauxiliary capacitance electrode Cs can easily maintain a predeterminedvoltage. Further, since the low-impedance line 40 is located in theaperture of the pixel, it can serve as a dummy line 15L4 for adjustingthe aperture ratio of the pixel. Further, in this implementation, thelow-impedance line 40 is located in the source line layer 15 such thatno mask pattern for forming the low-impedance line 40 is necessary. Thisreduces manufacturing costs compared with implementations where alow-impedance line 40 is provided in a different layer.

(15-3: Example Arrangement 3)

The above Example Arrangements 1 and 2 describe implementations where alow-impedance line 40 is provided in a pixel in which a dummy line 15L4is provided; an implementation where a low-impedance 40 is providedregardless of whether a dummy line 15L4 is provided in the pixel or notwill be described.

FIG. 83A is a schematic diagram of a pixel of such an arrangement. Inthe implementation of this drawing, a low-impedance line 40 is locatedin the light-shielding region BM and extends generally parallel to thegate line 13G, and the ends of the low-impedance line 40 areelectrically connected with the auxiliary capacitance line CsL along theperiphery of the auxiliary capacitance electrode Cs shown in FIG. 80. Inthis drawing, the auxiliary capacitance electrode Cs and the elementsconstituting parts of the gate driver 11 including the dummy line 15L4or line 15L1 are not shown.

FIG. 83B is a cross-sectional view of the pixel PIX of FIG. 83A takenalong line C-C. As shown in FIG. 83B, a low-impedance line 40 andauxiliary capacitance electrode Cs are provided on top of the protectionfilm 23, and the auxiliary capacitance electrode Cs is in contact withthe low-impedance line 40. Thus, as the low-impedance line 40 isprovided in the light-shielding region BM, it can also be provided in apixel in which an element constituting a part of a gate driver 11 isprovided without decreasing the aperture ratio of the pixel. Thus, evenwhen the potential of an auxiliary capacitance electrode Cs near a line15L1, which is particularly susceptible to noise of the line 15L1, isdisplaced from a predetermined level, the potential of this auxiliarycapacitance electrode Cs can return to the predetermined level.

(15-4: Example Arrangement 4)

In the above implementation of FIG. 83B, the auxiliary capacitanceelectrode Cs is located on top of the low-impedance line 40 such thatthe low-impedance line 40 and auxiliary capacitance electrode Cs are incontact with each other; alternatively, other arrangements are possibleas long as the auxiliary capacitance electrode Cs and low-impedance line40 are in contact with each other, as in the following implementation.

FIG. 83C is a cross-sectional view of the pixel PIX of FIG. 83A takenalong line C-C. As shown in FIG. 83C, the low-impedance line 40 islocated in the gate layer 13, i.e. in the same layer as the gate line13G. On top of the gate layer 13 are stacked a gate insulating film 21and protection films 22 and 23, and a contact hole CH is formed in thegate insulating film 21 and protection films 22 and 23 to extendtherethrough to the surface of the low-impedance line 40. An auxiliarycapacitance electrode Cs is provided on top of the protection film 23,and the low-impedance line 40 is connected with the auxiliarycapacitance electrode Cs via the contact hole CH. Similar to theimplementation of FIG. 83B, this arrangement makes it easier tomaintain, at a predetermined level, the potential of the auxiliarycapacitance electrode Cs in a pixel in which an element constituting apart of a gate driver 11 is provided, without reducing the apertureratio of the pixel.

(16) The above first to fifteenth embodiments describe implementationswhere the elements constituting gate drivers 11 are provided in thedisplay region; however, only the elements constituting the drivingcircuits for controlling the potentials of those signal lines crossingthe data lines that share at least one function are required to beprovided in the display region. Only at least one of the elementsconstituting each of the gate drivers 11, 11_A, 11_B, 11_1 and 11_2, atleast one of the elements constituting each of the CS drivers 80, or atleast one of the elements constituting each of the EL drivers 93 arerequired to be provided in the display region.

INDUSTRIAL APPLICABILITY

The present invention is industrially useful as a display deviceincluding an active-matrix substrate.

1. An active-matrix substrate comprising: a plurality of data lines; aplurality of lines crossing the plurality of data lines and including atleast gate lines; and a driving circuit connected with at least one ofthe plurality of lines for controlling a potential of this line inresponse to a control signal supplied from outside a display region thatincludes pixel regions defined by the data lines and the gate lines, thedriving circuit including a plurality of switching elements, at leastone of the plurality of switching elements being located in the pixelregions; wherein the plurality of switching elements located in thepixel regions includes a first switching element and a second switchingelement located in two of the pixel regions, respectively.
 2. Theactive-matrix substrate according to claim 1, wherein the firstswitching element and the second switching element are connected inparallel.
 3. The active-matrix substrate according to claim 1, furthercomprising a plurality of control signal lines located in the displayregion, a plurality of control signals including a clock signal, a resetsignal and a power supply voltage signal being supplied to the pluralityof control signal lines, wherein the driving circuit is connected withat least one of the gate lines and is connected with the plurality ofcontrol signal lines for controlling a potential of the at least onegate line by applying one of a selection voltage and a non-selectionvoltage in response to the control signal supplied via the plurality ofcontrol signal lines, and the gate lines cross the data lines, and thecontrol signal lines are generally parallel to the data lines.
 4. Theactive-matrix substrate according to claim 1, further comprising: apixel electrode located in one of the pixel regions and connected withone of the gate lines and one of the data lines, wherein a shield layermade of conductive film is provided between one of the switchingelements of the driving circuit that is located in the pixel regions,and the pixel electrode.
 5. The active-matrix substrate according toclaim 1, further comprising: a pixel electrode located in one of thepixel regions and connected with one of the gate lines and one of thedata lines, wherein one of the switching elements of the driving circuitthat is located in the pixel regions is disposed so as not to overliethe pixel electrode.
 6. The active-matrix substrate according to claim1, wherein an adjustment line is further provided in a pixel region inwhich the switching element of the driving circuit is not provided suchthat this pixel region has an aperture ratio substantially equal to thatof a pixel region in which a switching element of the driving circuit isprovided.
 7. The active-matrix substrate according to claim 6, whereinthe adjustment line is an auxiliary capacitance line.
 8. Theactive-matrix substrate according to claim 3, wherein at least a portionof the control signal lines is disposed to be generally parallel to thedata lines and located at generally the same distance from two datalines in the pixel regions.
 9. The active-matrix substrate according toclaim 1, wherein a pixel region in which a switching element of thedriving circuit is provided has a larger dimension measured in adirection in which the gate lines extend than other pixel regions. 10.The active-matrix substrate according to claim 1, wherein each of thepixel regions includes a pixel electrode connected with one of the gatelines and one of the data lines; and an auxiliary capacitance electrodeconnected with the pixel electrode, the active-matrix substrate furthercomprising: an auxiliary capacitance line located outside the displayregion and connected with the auxiliary capacitance electrode forsupplying a predetermined potential to the auxiliary capacitanceelectrode; and a low-impedance line located in the pixel regions andconnected with the auxiliary capacitance electrode and connected withthe auxiliary capacitance line.
 11. The active-matrix substrateaccording to claim 1, wherein a plurality of driving circuits areprovided, each for one of the gate lines.
 12. The active-matrixsubstrate according to claim 1, wherein the driving circuit is providedin each of K regions (K is a natural number, K≧2) arranged in adirection in which the gate lines of the display region extend, eachdriving circuit being provided for every K gate lines, driving circuitsbeing provided on different gate lines in different regions.
 13. Theactive-matrix substrate according to claim 3, wherein the pixel regionscorresponds to a plurality of colors, and the plurality of controlsignal lines are provided in pixel regions corresponding to one of theplurality of colors.
 14. The active-matrix substrate according to claim1, wherein a pixel region in which a switching element of the drivingcircuit is provided has a lager dimension measured in a direction inwhich at least one of the gate line and the data line extends than otherpixel regions.
 15. The active-matrix substrate according to claim 1,wherein the driving circuit is connected with one of the gate lines andcontrols the potential of this gate line by applying one of a selectionvoltage and a non-selection voltage to the gate line in response to thecontrol signal, and the display region is divided into a plurality ofsub-regions arranged in a direction in which the gate lines arearranged, and the driving circuit provided for the gate line disposed ineach of the plurality of sub-regions applies one of the selectionvoltage and the non-selection voltage to the gate line at a frequencythat is specified for the sub-region.
 16. The active-matrix substrateaccording to claim 1, wherein the lines include the gate lines andlight-emission control lines, the pixel region includes a light-emittingelement, an electric circuit connected with one of the data lines andone of the gate lines, and a light-emission control switching elementhaving a gate terminal connected with one of the light-emission controllines, a source terminal connected with the electric circuit, and adrain terminal connected with the light-emitting element, the drivingcircuit includes light-emission control line drivers each provided forone of the light-emission control lines for controlling a potential ofthe light-emission control line in response to the control signal. 17.The active-matrix substrate according to claim 1, wherein a plurality ofthe driving circuits are provided for a plurality of the gate lines tocontrol a potential of the gate lines; and the switching elementsincluded in two driving circuits of adjacent rows of the gate lines arearranged such that the switching elements included in the drivingcircuit of an upper row of the gate lines are horizontally displacedfrom the switching elements included in the driving circuit of a lowerrow of the gate lines.
 18. A display panel comprising: the active-matrixsubstrate according to claim 1; a counter-substrate having a colorfilters and a counter-electrode; and a liquid crystal layer sandwichedbetween the active-matrix substrate and the counter-substrate.
 19. Adisplay panel comprising: the active-matrix substrate according to claim1; a counter-substrate having a color filter; and a liquid crystal layersandwiched between the active-matrix substrate and thecounter-substrate.
 20. The display panel according to claim 18, whereinat least one element of the driving circuit is provided on theactive-matrix substrate in a dark-line region that is produced dependingon orientation in the liquid crystal layer within the pixel regions.